article

A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC

Authors:

Peter F. Curran,

Russell P. Kraft,

John F. McDonaldAuthors Info & Claims

Integration, the VLSI Journal, Volume 38, Issue 3

Pages 525 - 540

Published: 01 January 2005 Publication History

Abstract

This paper describes the implementation of a scalable SiGe FPGA that serves as an interleaving and deinterleaving block in a high-speed reconfigurable data acquisition system. In this paper, the different generations of SiGe configurable blocks (Basic Cells(BC)) evolved from the Xilinx 6200 are presented and measured. The latest generation has a 94% reduction in power consumption (from 71 to 4.2mW) and an 82.5% reduction of the propagation delay (from 238 to 42 ps) compared to the first generation design. To demonstrate the SiGe FPGA's capabilities of handling gigahertz signals, the SiGe FPGAs configured as the 4:1 multiplexer and 1:4 demultiplexer were designed to run at 10 Gbps. The comparisons between the SiGe and CMOS FPGAs are also provided. With these design results, the SiGe FPGA is able to process gigahertz signals such as S and K microwave bands.

References

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Digital Library

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Cited By

Guo JYou CChu MErdogan OKraft RMcDonald J(2005)A High Speed Reconfigurable Gate Array for Gigahertz ApplicationsProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.8(124-129)Online publication date: 11-May-2005
https://dl.acm.org/doi/10.1109/ISVLSI.2005.8

Index Terms

A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

cover image Integration, the VLSI Journal

Integration, the VLSI Journal Volume 38, Issue 3

Special issue: ACM great lakes symposium on VLSI

January 2005

255 pages

ISSN:0167-9260

Issue’s Table of Contents

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Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 January 2005

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Cited By

Guo JYou CChu MErdogan OKraft RMcDonald J(2005)A High Speed Reconfigurable Gate Array for Gigahertz ApplicationsProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.8(124-129)Online publication date: 11-May-2005
https://dl.acm.org/doi/10.1109/ISVLSI.2005.8

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