Systolic array

The systolic array architecture is one of the most popular choices for convolutional neural network hardware accelerators. The biggest advantage of the systolic array architecture is its simple and efficient design principle. Without complicated control ...

Using a directed acyclic graph (DAG) model of algorithms, the authors focus on processor-time-minimal multiprocessor schedules: time-minimal multiprocessor schedules that use as few processors as possible. The Kung, Lo, and Lewis (KLL) algorithm for ...

To improve the performance of systolic array processors, this paper designs and implements a novel architecture which supports dynamic dataflows. First, we design three typical systolic array processors, including the output stationary,...

• This paper designs and implements a novel architecture which supports dynamic dataflows.