- Authors:
- Paolo Ienne,
- Rainer Leupers
Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization. This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include "as is" in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor. · First book to present comprehensively the major ASIP design methodologies and tools without any particular bias. · Written by most of the pioneers and top international experts of this young domain. · Unique mix of management perspective, technical detail, research outlook, and practical implementation.
Cited By
- Hussein E, Waschneck B and Mayr C (2024). Automating application-driven customization of ASIPs, Journal of Systems Architecture: the EUROMICRO Journal, 148:C, Online publication date: 1-Mar-2024.
- Li T, Shafique M, Ambrose J, Henkel J and Parameswaran S (2017). Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors, IEEE Transactions on Computers, 66:4, (647-660), Online publication date: 1-Apr-2017.
- Wang C, Li X, Zhang H, Wang A and Zhou X (2017). Hot spots profiling and dataflow analysis in custom dataflow computing SoftProcessors, Journal of Systems and Software, 125:C, (427-438), Online publication date: 1-Mar-2017.
- Dehyadegari M, Marongiu A, Kakoee M, Mohammadi S, Yazdani N and Benini L (2015). Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators, IEEE Transactions on Computers, 64:8, (2132-2144), Online publication date: 1-Aug-2015.
Eusse J, Williams C and Leupers R (2015). CoEx, ACM Transactions on Reconfigurable Technology and Systems, 8:3, (1-16), Online publication date: 19-May-2015.- Eusse J, Leupers R, Ascheid G, Sudowe P, Leibe B and Sadasue T A flexible ASIP architecture for connected components labeling in embedded vision applications Proceedings of the conference on Design, Automation & Test in Europe, (1-6)
- Thomas P, Martin G, Heine D, Moolenaar D and Kim J Configurability in IP subystems Proceedings of the Conference on Design, Automation and Test in Europe, (163-168)
- Murray A and Franke B Compiling for automatically generated instruction set extensions Proceedings of the Tenth International Symposium on Code Generation and Optimization, (13-22)
- Stojilović M, Novo D, Saranovac L, Brisk P and Ienne P Selective flexibility Proceedings of the Conference on Design, Automation and Test in Europe, (1543-1548)
- Grad M and Plessl C (2012). On the feasibility and limitations of just-in-time Instruction set extension for FPGA-based reconfigurable processors, International Journal of Reconfigurable Computing, 2012, (1-1), Online publication date: 1-Jan-2012.
- Galuzzi C and Bertels K (2011). The Instruction-Set Extension Problem, ACM Transactions on Reconfigurable Technology and Systems, 4:2, (1-28), Online publication date: 1-May-2011.
- Hameed R, Qadeer W, Wachs M, Azizi O, Solomatnikov A, Lee B, Richardson S, Kozyrakis C and Horowitz M (2010). Understanding sources of inefficiency in general-purpose chips, ACM SIGARCH Computer Architecture News, 38:3, (37-47), Online publication date: 19-Jun-2010.
- Hameed R, Qadeer W, Wachs M, Azizi O, Solomatnikov A, Lee B, Richardson S, Kozyrakis C and Horowitz M Understanding sources of inefficiency in general-purpose chips Proceedings of the 37th annual international symposium on Computer architecture, (37-47)
- Leupers R and Castrillon J MPSoC programming using the MAPS compiler Proceedings of the 2010 Asia and South Pacific Design Automation Conference, (897-902)
- Castrillon J, Zhang D, Kempf T, Vanthournout B, Leupers R and Ascheid G Task management in MPSoCs Proceedings of the 2009 International Conference on Computer-Aided Design, (587-594)
- Li T, Sun Z, Jigang W and Lu X Fast enumeration of maximal valid subgraphs for custom-instruction identification Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems, (29-36)
- Kluter T, Brisk P, Ienne P and Charbon E Way Stealing Proceedings of the 46th Annual Design Automation Conference, (31-36)
- Kluter T, Brisk P, Ienne P and Charbon E Speculative DMA for architecturally visible storage in instruction set extensions Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, (243-248)
- Martin G (2008). What is a configurable, extensible processor?, ACM SIGDA Newsletter, 38:17, (1-1), Online publication date: 1-Sep-2008.
- Martin G (2008). What is a configurable, extensible processor?, ACM SIGDA Newsletter, 38:16, (1-1), Online publication date: 15-Aug-2008.
- Muhammad R, Apvrille L and Pacalet R Evaluation of ASIPs Design with LISATek Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, (177-186)
- Karuri K, Chattopadhyay A, Hohenauer M, Leupers R, Ascheid G and Meyr H Increasing data-bandwidth to instruction-set extensions through register clustering Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, (166-171)
- Schuster T, Bougard B, Raghavan P, Priewasser R, Novo D, Van der Perre L and Catthoor F Design of a low power pre-synchronization ASIP for multimode SDR terminals Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation, (322-332)
- Huynh H and Mitra T Instruction-set customization for real-time embedded systems Proceedings of the conference on Design, automation and test in Europe, (1472-1477)
- Shen Z, He H, Zhang Y and Sun Y (2007). A video specific instruction set architecture for ASIP design, VLSI Design, 2007:2, (1-7), Online publication date: 1-Apr-2007.
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