Article

General purpose operating system support for multiple page sizes

Authors:

Narayanan Ganapathy,

Curt SchimmelAuthors Info & Claims

ATEC '98: Proceedings of the annual conference on USENIX Annual Technical Conference

Page 8

Published: 15 June 1998 Publication History

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Abstract

Many commercial microprocessor architectures support translation lookaside buffer (TLB) entries with multiple page sizes. This support can be used to substantially reduce the overhead introduced by TLB misses incurred when the processor runs an application with a large working set. Applications are currently not able to take advantage of this hardware feature because most commercial operating systems support only one page size. In this paper we present a design that provides general purpose operating system support that allows applications to use multiple page sizes. The paper describes why providing this support is not as simple as it first seems. If not designed carefully, adding this support will require significant modifications and add a lot of overhead to the operating system. The paper shows how our approach simplifies the design without sacrificing functionality and performance. In addition, applications need not be modified to make use of this feature. The design has been implemented on IRIX 6.4 operating system running on the SGI Origin platform. We include some performance results at the end to show how our design allows applications to take advantage of large pages to gain performance improvements.

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Cited By

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Jia WZhang JShan JDu YDing XXu T(2023)HugeGPT: Storing Guest Page Tables on Host Huge Pages to Accelerate Address TranslationProceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT58117.2023.00014(62-73)Online publication date: 21-Oct-2023
https://dl.acm.org/doi/10.1109/PACT58117.2023.00014
Shang XJia WShan JDing X(2021)CoPlace: Effectively Mitigating Cache Conflicts in Modern CloudsProceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT52795.2021.00027(274-288)Online publication date: 26-Sep-2021
https://dl.acm.org/doi/10.1109/PACT52795.2021.00027
Vavouliotis GAlvarez LKarakostas VNikas KKoziris NJiménez DCasas MMartínez JDuato JJohn L(2021)Exploiting page table locality for agile TLB prefetchingProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00016(85-98)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00016
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Index Terms

General purpose operating system support for multiple page sizes
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
2. Software and its engineering
  1. Software creation and management
    1. Software verification and validation
      1. Operational analysis
  2. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Allocation / deallocation strategies
        Virtual memory

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ATEC '98: Proceedings of the annual conference on USENIX Annual Technical Conference

June 1998

476 pages

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USENIX Association

United States

Publication History

Published: 15 June 1998

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Jia WZhang JShan JDu YDing XXu T(2023)HugeGPT: Storing Guest Page Tables on Host Huge Pages to Accelerate Address TranslationProceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT58117.2023.00014(62-73)Online publication date: 21-Oct-2023
https://dl.acm.org/doi/10.1109/PACT58117.2023.00014
Shang XJia WShan JDing X(2021)CoPlace: Effectively Mitigating Cache Conflicts in Modern CloudsProceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT52795.2021.00027(274-288)Online publication date: 26-Sep-2021
https://dl.acm.org/doi/10.1109/PACT52795.2021.00027
Vavouliotis GAlvarez LKarakostas VNikas KKoziris NJiménez DCasas MMartínez JDuato JJohn L(2021)Exploiting page table locality for agile TLB prefetchingProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00016(85-98)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00016
Achermann RPanwar ABhattacharjee ARoscoe TGandhi JLarus JCeze LStrauss K(2020)Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory MachinesProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378468(283-300)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.1145/3373376.3378468
Hu JBai XSha SLuo YWang XWang ZJacob B(2018)HUBProceedings of the International Symposium on Memory Systems10.1145/3240302.3240420(31-37)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3240302.3240420
Alam HZhang TErez MEtsion Y(2017)Do-It-Yourself Virtual Memory TranslationACM SIGARCH Computer Architecture News10.1145/3140659.308020945:2(457-468)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080209
Marathe YGulur NRyoo JSong SJohn LHunter HMoreno JEmer JSanchez D(2017)CSALTProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3124549(449-462)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3124549
Alam HZhang TErez MEtsion Y(2017)Do-It-Yourself Virtual Memory TranslationProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080209(457-468)Online publication date: 24-Jun-2017
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Gandhi JHill MSwift M(2016)Agile pagingACM SIGARCH Computer Architecture News10.1145/3007787.300121244:3(707-718)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001212
Gandhi JHill MSwift MMin SLoh G(2016)Agile pagingProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.67(707-718)Online publication date: 18-Jun-2016
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Practical, transparent operating system support for superpages

Efficient Address Translation for Architectures with Multiple Page Sizes

Efficient Address Translation for Architectures with Multiple Page Sizes

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