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Implementing Signatures for Transactional Memory

Published: 01 December 2007 Publication History

Abstract

Transactional Memory (TM) systems must track the read and write sets--items read and written during a transaction--to detect conflicts among concurrent trans- actions. Several TMs use signatures, which summarize unbounded read/write sets in bounded hardware at a per- formance cost of false positives (conflicts detected when none exists). This paper examines different organizations to achieve hardware-efficient and accurate TM signatures. First, we find that implementing each signature with a single k-hash- function Bloom filter (True Bloom signature) is inefficient, as it requires multi-ported SRAMs. Instead, we advocate using k single-hash-function Bloom filters in parallel (Par- allel Bloom signature), using area-efficient single-ported SRAMs. Our formal analysis shows that both organiza- tions perform equally well in theory and our simulation- based evaluation shows this to hold approximately in prac- tice. We also show that by choosing high-quality hash func- tions we can achieve signature designs noticeably more ac- curate than the previously proposed implementations. Fi- nally, we adapt Pagh and Rodler's cuckoo hashing to im- plement Cuckoo-Bloom signatures. While this representa- tion does not support set intersection, it mitigates false pos- itives for the common case of small read/write sets and per- forms like a Bloom filter for large sets.

Cited By

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  • (2019)FPGA-Accelerated Optimistic Concurrency Control for Transactional MemoryProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358270(911-923)Online publication date: 12-Oct-2019
  • (2019)CoNDAProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322266(629-642)Online publication date: 22-Jun-2019
  • (2019)Reducing Writebacks Through In-Cache DisplacementACM Transactions on Design Automation of Electronic Systems10.1145/328918724:2(1-21)Online publication date: 10-Jan-2019
  • Show More Cited By

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  1. Implementing Signatures for Transactional Memory

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      cover image ACM Conferences
      MICRO 40: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
      December 2007
      435 pages
      ISBN:0769530478

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      IEEE Computer Society

      United States

      Publication History

      Published: 01 December 2007

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      MICRO 40 Paper Acceptance Rate 35 of 166 submissions, 21%;
      Overall Acceptance Rate 484 of 2,242 submissions, 22%

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      View all
      • (2019)FPGA-Accelerated Optimistic Concurrency Control for Transactional MemoryProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358270(911-923)Online publication date: 12-Oct-2019
      • (2019)CoNDAProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322266(629-642)Online publication date: 22-Jun-2019
      • (2019)Reducing Writebacks Through In-Cache DisplacementACM Transactions on Design Automation of Electronic Systems10.1145/328918724:2(1-21)Online publication date: 10-Jan-2019
      • (2018)TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual CachesIEEE Computer Architecture Letters10.1109/LCA.2017.271214017:1(17-20)Online publication date: 1-Jan-2018
      • (2017)HAShCacheACM Transactions on Architecture and Code Optimization10.1145/315864114:4(1-26)Online publication date: 18-Dec-2017
      • (2017)FractalACM SIGARCH Computer Architecture News10.1145/3140659.308021845:2(587-599)Online publication date: 24-Jun-2017
      • (2017)FractalProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080218(587-599)Online publication date: 24-Jun-2017
      • (2017)Leveraging irrevocability to deal with signature saturation in hardware transactional memoryThe Journal of Supercomputing10.1007/s11227-016-1944-z73:6(2525-2557)Online publication date: 1-Jun-2017
      • (2016)Probabilistic Directed Writebacks for Exclusive CachesACM SIGARCH Computer Architecture News10.1145/2971331.297133444:1(9-18)Online publication date: 12-Jul-2016
      • (2016)A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction ExecutionACM Transactions on Architecture and Code Optimization10.1145/283702812:4(1-26)Online publication date: 4-Jan-2016
      • Show More Cited By

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