Browse Theses

Simulation is the primary tool for validation and analysis of digital circuits in VLSI design. As the complexity of VLSI circuits has increased, distributed event-driven simulation has attracted considerable interest for providing fast simulation. In this thesis, based on the characteristics of gate-level logic simulation, we study efficient paradigms and data structures for fast parallel logic simulation on massively parallel SIMD (Single Instruction Multiple Data) machines. The performance of the proposed schemes is measured on the CM-2 (Connection Machine) and the MP-1 (MasPar) in terms of number of simulation cycles, parallelism, maximum event queue sizes, and execution times. We present a probabilistic model to estimate the performance of parallel logic simulation when a processor contains more than one gate. The performance estimation shows that parallelism and processor utilization increase as the number of gates per processor increases. We propose new parallel logic simulation techniques by giving a clock advancement window to each gate in conservative simulation and optimistic simulation. Experimental results show that the techniques give much better performance than traditional simulation techniques since the new techniques enhance simulation clock advancements. We present a distributed token driven logic simulation technique as a parallelized version of compiled-code logic simulation which is used to verify the functional correctness very efficiently. This thesis presents broad studies of parallel logic simulation in massively parallel SIMD environments. The research results are useful in the implementation of parallel logic simulation, as a part of VLSI design, in SIMD processing environments.