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Path selection for monitoring unexpected systematic timing effects

Published: 19 January 2009 Publication History

Abstract

This paper presents a novel path selection methodology to select paths for monitoring unexpected systematic timing effects. The methodology consists of three components: path filtering, path encoding, and path clustering. Given a large set of critical paths, in path filtering, the goal is to filter out paths that cannot be functionally sensitized. To explore the space of unexpected timing effects, a set of features are defined to encode paths into path vectors. Each feature is a source of concern that may potentially contribute to the cause of an unexpected timing effect. Finally, a kernel-based clustering algorithm is employed to group similar path vectors into clusters from which the best representative paths are selected for post-silicon monitoring. The effectiveness of our proposed methodology is demonstrated through experiments on an industrial ASIC design.

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Cited By

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  • (2015)Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path SelectionACM Transactions on Design Automation of Electronic Systems10.1145/274623720:3(1-23)Online publication date: 24-Jun-2015
  • (2010)NIMProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871256(1373-1376)Online publication date: 8-Mar-2010
  • (2010)Representative path selection for post-silicon timing prediction under variabilityProceedings of the 47th Design Automation Conference10.1145/1837274.1837371(386-391)Online publication date: 13-Jun-2010
  • Show More Cited By
  1. Path selection for monitoring unexpected systematic timing effects

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    Published In

    cover image ACM Conferences
    ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference
    January 2009
    902 pages
    ISBN:9781424427482

    Sponsors

    • IEEE Circuits and Systems Society
    • SIGDA: ACM Special Interest Group on Design Automation
    • IPSJ SIGSLDM: Information Processing Society of Japan - SIG System LSI Design Methodology
    • IEICE ESS: Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society

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    IEEE Press

    Publication History

    Published: 19 January 2009

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    ASPDAC '09
    Sponsor:
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    • IPSJ SIGSLDM
    • IEICE ESS

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    Overall Acceptance Rate 466 of 1,454 submissions, 32%

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    View all
    • (2015)Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path SelectionACM Transactions on Design Automation of Electronic Systems10.1145/274623720:3(1-23)Online publication date: 24-Jun-2015
    • (2010)NIMProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871256(1373-1376)Online publication date: 8-Mar-2010
    • (2010)Representative path selection for post-silicon timing prediction under variabilityProceedings of the 47th Design Automation Conference10.1145/1837274.1837371(386-391)Online publication date: 13-Jun-2010
    • (2010)Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variationsProceedings of the 47th Design Automation Conference10.1145/1837274.1837344(274-279)Online publication date: 13-Jun-2010

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