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A DSP-enhanced 32-bit embedded microprocessor

Published: 01 January 2009 Publication History

Abstract

EISC (Extendable Instruction Set Computer) is a compressed code architecture developed for embedded applications. In this paper, we propose a DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the weaknesses, of the EISC architecture to accelerate DSP applications with a relatively low hardware overhead. Our simulations and experiments show that the proposed DSP-enhanced processor reduces the average execution times of the DSP kernels and DSP applications considered in this work, by 42.5% and 31.3% respectively. The proposed DSP enhancements cost about 10300 gates and do not affect the operating frequency of the processor. The proposed DSP-enhanced processor has been embedded in an SoC for video processing and proven in silicon.

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Reviews

Junqing Sun

High-performance computer architectures for specific applications are widely discussed. Applications such as digital signal processing (DSP), climate simulation, biology computation, and structural analysis can require tremendous computation efforts, from embedded systems to supercomputers. As computation time is crucial to the success and cost of these important projects, higher performance architectures for these applications are as important as they are for general-purpose computers. There are multiple alternatives to achieve this goal. For example, field-programmable gate arrays (FPGAs), graphics processing units (GPUs), and cell processors are usually adopted as coprocessors that work with the central processing units (CPUs) to accelerate the computation. Normally, these architectures require special programming abilities. For example, FPGA accelerator designers need to have good knowledge of hardware and design-specific processor architectures, for the best performance of certain applications. This paper targets DSP applications, by extending the instruction set of embedded processors. The great thing about it is that the users can take advantage of this high-performance DSP unit by simply using a DSP instruction. The results show significant improvement, compared to traditional processors. This is a very well-written paper, with very clear figures. Kim and Oh provide examples for their design. Online Computing Reviews Service

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Information

Published In

cover image Journal of Embedded Computing
Journal of Embedded Computing  Volume 3, Issue 1
Selected papers of EUC 2005
January 2009
82 pages

Publisher

IOS Press

Netherlands

Publication History

Published: 01 January 2009

Author Tags

  1. DSP-enhanced microprocessor
  2. SIMD
  3. embedded microprocessor
  4. hardware address generator
  5. register extension

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