Low area - scalable hardware/software co-design for elliptic curve cryptography
Pages 168 - 172
Abstract
The contribution in this paper describes a solution to implement a low cost-low area scalable elliptic curve cryptography (ECC) over binary finite fields GF(2m) using a hardware-software co-design approach. The proposed hardware-software co-design is hosted on a freesoft-core processor from Xilinx FPGA, namely PicoBlaze as a low-cost platform. The PicoBlaze is supported by two novel circuits to execute the underlying arithmetic over GF(2m). Scalability is explored and a novel architecture is presented in this work that scales for the set of curves recommended by the ECC standards, namely, m=113,131,163,193 with minimal area overheads whilst achieving practical performance. The proposed hardware-software co-design is parameterised for 8, 16, and 32 bit data widths. The implementation of the scalable ECC processor consumes only 341 and 473 slices of the lowest cost chips from Xilinx Spartan III family namely XC3S50 for the 8 and 16 bits data paths implementations and 1041 slices of the XC3S200 device for the 32 bit data path.
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- Low area - scalable hardware/software co-design for elliptic curve cryptography
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