research-article

An analytical method for evaluating network-on-chip performance

Authors:

Sahar Foroutan,

Yvain Thonnart,

Richard Hersemeule,

Ahmed JerrayaAuthors Info & Claims

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 1629 - 1632

Published: 08 March 2010 Publication History

Abstract

Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and become larger and larger. While on-chip system designers must be able to get fast and accurate communication performance analysis for such huge systems, the simulation-based approaches are not adequate anymore. Addressing the increasing need for early performance evaluation in NoC-based system design flow, this paper presents a generic analytical method to estimate communication latencies and link-buffer utilizations for a given NoC architecture with a given application mapped on it. The accuracy of our method is experimentally compared with the results obtained from Cycle-Accurate SystemC simulations.

References

[1]

K. Goossens, J. Dielissen, and A. Radulescu, "AEthereal Network on Chip: Concepts, Architectures, and Implementations," IEEE Des. Test, vol. 22, pp. 414--421, 2005.

Digital Library

[2]

T. Bjerregaard, "The MANGO Clockless Network-on-Chip: Concepts and Implementation." vol. PhD thesis: Technical University of Denmark, 2005.

[3]

E. Beigne, F. Clermidy, P. Vivet, A. Clouard, and M. Renaudin, "An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework," in Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems: IEEE Computer Society, 2005.

Digital Library

[4]

M. Coppola, M. D. Grammatikakis, R. Locatelli, G. Maruccia, and L. Pieralisi, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC, 2008.

Digital Library

[5]

L. Benini, D. Bertozzi, D. Bruni, N. Drago, F. Fummi, and M. Poncino, "Legacy SystemC co-simulation of multi-processor systems-on-chip," 2002, pp. 494--499.

Digital Library

[6]

S. G. Pestana, E. Rijpkema, A. Radulescu, K. Goossens, and O. P. Gangwal, "Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach," in Proceedings of the conference on Design, automation and test in Europe - Volume 2: IEEE Computer Society, 2004.

Digital Library

[7]

A. Sheibanyrad, I. Miro Panades, and A. Greiner, "Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture," in Design Automation and Test in Europe (DATE) Nice, France: EDA Consortium (IEEE, ACM), 2007, pp. 1090--1095.

Digital Library

[8]

P. Hu and L. Kleinrock, "An analytical model for wormhole routing with finite size input buffers," 1997, pp. 549--560.

[9]

A. E. Kiasari, D. Rahmati, H. Sarbazi-Azad, and S. Hessabi, "A Markovian Performance Model for Networks-on-Chip," 2008, pp. 157--164.

Digital Library

[10]

W. J. Guan, W. K. Tsai, and D. Blough, "An analytical model for wormhole routing in multicomputerinterconnection networks," 1993, pp. 650--654.

[11]

U. Y. Ogras and R. Marculescu, "Analytical router modeling for networks-on-chip performance analysis," 2007, pp. 1--6.

[12]

W. J. Dally, "Performance analysis of k-ary n-cube interconnection networks," IEEE Transactions on Computers, vol. 39, pp. 775--785, 1990.

Digital Library

[13]

A. Khonsari, M. Ould-Khaoua, and J. Ferguson, "A General Analytical Model of Adaptive Wormhole Routing in k-Ary n-Cube Interconnection Networks," SIMULATION SERIES, vol. 35, pp. 547--554, 2003.

[14]

Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "Network Delays and Link Capacities in Application-Specific Wormhole NoCs," Special Issue of the Journal of VLSI Design, 2007.

[15]

E. Salminen, A. Kulmala, and T. D. Hamalainen, "On network-on-chip comparison," in DSD 2007. 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, 2007.

Digital Library

[16]

W. J. Dally, Principles and practices of interconnection networks: Morgan Kaufmann, 2004.

Digital Library

[17]

E. Salminen, A. Kulmala, and T. D. Hamalainen, "On network-on-chip comparison," 2007, pp. 503--510.

Digital Library

Cited By

Weldezion AGrange MJantsch ATenhunen HPamunuwa D(2015)Zero-load predictive model for performance analysis in deflection routing NoCsMicroprocessors & Microsystems10.1016/j.micpro.2015.09.00239:8(634-647)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.09.002
Kiasari AJantsch ALu Z(2013)Mathematical formalisms for performance evaluation of networks-on-chipACM Computing Surveys10.1145/2480741.248075545:3(1-41)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2480741.2480755
Foroutan SSheibanyrad APétrot FGroeneveld PSciuto DHassoun S(2012)Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfacesProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228427(366-375)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228427
Show More Cited By

Recommendations

An analytical approach for network-on-chip performance analysis

Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little ...
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate ...
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

March 2010

1868 pages

ISBN:9783981080162

General Chairs:
Giovanni De Micheli
EPF Lausanne, CH
,
Bashir Al-Hashimi
University of Southampton, UK
,
Program Chairs:
Wolfgang Mueller
University of Paderborn, SE
,
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

Check for updates

Qualifiers

Research-article

Conference

DATE '10

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '10: Design, Automation and Test in Europe

March 8 - 12, 2010

Germany, Dresden

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
84
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Weldezion AGrange MJantsch ATenhunen HPamunuwa D(2015)Zero-load predictive model for performance analysis in deflection routing NoCsMicroprocessors & Microsystems10.1016/j.micpro.2015.09.00239:8(634-647)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.09.002
Kiasari AJantsch ALu Z(2013)Mathematical formalisms for performance evaluation of networks-on-chipACM Computing Surveys10.1145/2480741.248075545:3(1-41)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2480741.2480755
Foroutan SSheibanyrad APétrot FGroeneveld PSciuto DHassoun S(2012)Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfacesProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228427(366-375)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228427
Ben-Itzhak YCidon IKolodny AMarculescu RKishinevsky MGinosar RChatha K(2011)Delay analysis of wormhole based heterogeneous NoCProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999972(161-168)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1999946.1999972
Papamichael MHoe JMutlu OMarculescu RKishinevsky MGinosar RChatha K(2011)FISTProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999969(137-144)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1999946.1999969
Grange MWeerasekera RPamunuwa DJantsch AWeldezion AMarculescu RKishinevsky MGinosar RChatha K(2011)Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networksProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999956(57-64)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1999946.1999956

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents