research-article

Testing TSV-based three-dimensional stacked ICs

Author:

Erik Jan MarinissenAuthors Info & Claims

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 1689 - 1694

Published: 08 March 2010 Publication History

Abstract

To meet customer's product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient. The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new generation of 'super chips'. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes and physical access limitations. This presentation focuses on the available solutions and still open challenges for testing 3D-SICs. It discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.

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Cited By

Maity DRoy SGiri C(2022)A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/351780818:4(1-23)Online publication date: 20-Apr-2022
https://dl.acm.org/doi/10.1145/3517808
Pei SZhang JJin YJin SLiu JXu WJones ALi HCoskun AMargala M(2015)An Effective TSV Self-Repair Scheme for 3D-Stacked ICsProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742071(21-26)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742071
Taouil MMasadeh MHamdioui SMarinissen EFettweis GNebel W(2014)Interconnect test for 3D stacked memory-on-logicProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616761(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616761
Show More Cited By

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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

March 2010

1868 pages

ISBN:9783981080162

General Chairs:
Giovanni De Micheli
EPF Lausanne, CH
,
Bashir Al-Hashimi
University of Southampton, UK
,
Program Chairs:
Wolfgang Mueller
University of Paderborn, SE
,
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

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DATE '10

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '10: Design, Automation and Test in Europe

March 8 - 12, 2010

Germany, Dresden

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Citations

Cited By

Maity DRoy SGiri C(2022)A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/351780818:4(1-23)Online publication date: 20-Apr-2022
https://dl.acm.org/doi/10.1145/3517808
Pei SZhang JJin YJin SLiu JXu WJones ALi HCoskun AMargala M(2015)An Effective TSV Self-Repair Scheme for 3D-Stacked ICsProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742071(21-26)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742071
Taouil MMasadeh MHamdioui SMarinissen EFettweis GNebel W(2014)Interconnect test for 3D stacked memory-on-logicProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616761(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616761
Chien JHsu RLin HYeh KChang S(2014)Contactless Stacked-die Testing for Pre-bond InterposersProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593111(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593111
Dev KWoods GReda S(2013)High-throughput TSV testing and characterization for 3D integration using thermal mappingProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488823(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488823
Marinissen ERosenstiel WMacii E(2012)Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493023(1277-1282)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493023
Pasca VAnghel LBenabdenbi M(2012)Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and DiagnosisJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5322-328:6(817-829)Online publication date: 1-Dec-2012
https://dl.acm.org/doi/10.1007/s10836-012-5322-3

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