simulating a PR-mesh on an larpbs
Page 261
Abstract
The unidirectional nature of propagation and predictable delays are two characteristics of optically pipelined buses that have made them popular in recent years. Many models have been proposed that use reconfigurable optically pipelined buses. In this paper we establish a relationship between a one dimensional and a two dimensional model of this type. This simulation shows that the challenge is to map the processors so that those belonging to a twodimensional bus segment are contiguous and in the same order on the simulating one-dimensional model. We focus on the Linear Array with a Reconfigurable Pipelined Bus System (LARPBS) and its two dimensional counterpart the Pipelined Reconfigurable Mesh (PR-Mesh).
References
[1]
R. Vaidynathan and J. L. Trahan, "Dynamic Reconfiguration: Architectures and Algorithms", Kluwer Pub., 2003.
[2]
Y. Pan and K. Li, "Linear array with a reconfigurable pipelined bus system: Concepts and applications", Inform. Sci. vol. 106, (1998), 237-258.
[3]
S. Q. Zheng and Y. Li, "Pipelined asynchronous time-division multiplexing optical bus", Opt. Eng. vol. 36, (1997), 3392-3400.
[4]
Y. Pan, "Order statistics on optically interconnected multiprocessor systems", Opt. Laser Tech. vol. 26, (1994), 281-287.
[5]
A. G. Bourgeois and J. L. Trahan, "Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses," International Journal on Foundations of Computer Science, vol. 11, (2000), pp. 553-571.
[6]
S. Pavel and S. G. Akl, "On the Power of Arrays with Optical Pipelined Buses", Proc. Int'l. Conf. Par. Distr. Proc. Techniques and Appl.", (1996), pp. 1443-1454.
[7]
M. Middendorf and H. ElGindy, "Matrix Multiplication on Processor Arrays with Optical Buses", Informatica, vol. 22, no. 3, (1998).
[8]
Z. Guo, "Optically Interconnected Processor Arrays with Switching Capability", Journal of Parallel and Distributed Computing vol. 23, (1994), pp. 314-329.
[9]
C. Qiao and R. Melhem, "Time-Division Optical Communicationsin Multiprocessor Arrays", IEEE Trans. Comput., vol. 42, (1993), pp. 577-590.
[10]
C. Qiao, "On Designing Communication-Intensive Algorithms for a Spanning Optical Bus Based Array", Parallel Processing Letters, vol. 5, (1995), pp. 499-511.
[11]
J. L. Trahan, A. G. Bourgeois, Y. Pan, and R. Vaidyanathan, "An Optimal and Scalable Algorithm for Permutation Routing on Reconfigurable Linear Arrays with Optically Pipelined Buses", Journal of Parallel and Distributed Computing, vol. 60, (2000), pp. 1125-1136.
[12]
A. Datta, "Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System", The Journal of Supercomputing, vol. 29, (2004), pp. 303-317.
[13]
J. L. Trahan, A. G. Bourgeois, and R. Vaidyanathan, "Tighter and Broader Complexity Results for Reconfigurable Models", Parallel Proccessing Letters, vol. 8, (1998), pp. 271-282.
[14]
S. Pavel and S.G Akl, "Integer Sorting and routing in arrays with reconfigurable optical buses", Proceedings of International Conference of Parallel Processing, pp. III-90-III-94, 1996.
- simulating a PR-mesh on an larpbs
Recommendations
Computing on the restricted LARPBS model
ISPA'03: Proceedings of the 2003 international conference on Parallel and distributed processing and applicationsMany algorithms have been designed on models using pipelined optical buses by several research groups. Linear array with a reconfigurable pipelined bus system (LARPBS) is one such model. The results in the literature show that most of the basic ...
Simulating a Mesh with Separable Buses by a Mesh with Partitioned Buses
ISPAN '99: Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and NetworksWe propose an algorithm that simulates a mesh with separable buses (MSB) by a mesh with partitioned buses (MPB). The MSB and the MPB are the two-dimensional mesh-connected computers which have additional broadcasting buses along every row and column. ...
Simulating SiScape: A Parallel CMP Architecture
AHS '08: Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and SystemsChip multiprocessors (CMPs) with a small number of cores are already a reality, while large scale CMPs are just on the horizon. CMPs are a straightforward architectural choice to exploit increased number of transistors, in an era of diminishing ...
Comments
Information & Contributors
Information
Published In
April 2006
399 pages
ISBN:1424400546
Sponsors
- IEEE CS TCPP: IEEE Computer Society Technical Committee on Parallel Processing
In-Cooperation
- IEEE TCCA: IEEE Computer Society Technical Committee on Computer Architecture
- SIGARCH: ACM Special Interest Group on Computer Architecture
- IEEE Computer Society Technical Committee on Distributed Processing
Publisher
IEEE Computer Society
United States
Publication History
Published: 25 April 2006
Check for updates
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 12 Nov 2024
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in