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Fast timing simulation of transient faults in digital circuits

Authors:

A. Dharchoudhury,

S. M. Kang,

H. Cha,

J. H. PatelAuthors Info & Claims

ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Pages 719 - 722

Published: 06 November 1994 Publication History

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Abstract

Transient fault simulation is an important verification activity for circuits used in critical applications since such faults account for over 80% of all system failures. This paper presents a timing level transient fault simulator that bridges the gap between electrical and gate-level transient fault simulators. A generic MOS circuit primitive and analytical solutions of node differential equations are used to perform transistor level simulation with accurate MOS-FET models. The transient fault is modeled by a piecewise quadratic injected current waveform; this retains the electrical nature of the transient fault and provides SPICE-like accuracy. Detailed comparisons with SPICE3 show the accuracy of this technique and speedups of two orders of magnitude are observed for circuits containing up to 2000 transistors. Latched error distributions of the benchmark circuits are also provided.

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Cited By

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Cao XXiao LLi JZhang RLiu SWang J(2019)A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442538:6(1109-1122)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834425
Chakrabarty KAlioto MBaas BBoon CChang MChang NChang YChang CChang SChen PChowdhury MCorsonello PElfadel IHamdioui SHashimoto MHo THomayoun HHwang YJoshi RKarnik TKermani MKim CKim TKulkarni JKursun ELarsson ELi HLi HMercier PMishra PNagata MNatarajan ANii KPande PSavidis ISeok MTan STehranipoor MTodri-Sanial AVelev MVelev MXu JZhang WZhang ZJackson S(2017)EditorialIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263857825:1(1-20)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2638578
Sheikh AEl-Maleh AElrabaa MSait S(2017)A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor RedundancyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.256953225:1(224-237)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2569532
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Index Terms

Fast timing simulation of transient faults in digital circuits
1. Hardware

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Published In

ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

November 1994

771 pages

ISBN:0897916905

Chairmen:
Jochen A. G. Jess
Eindhoven Univ. of Technology, Eindhoven, The Netherlands
,
Richard Rudell
Synopsys, Inc., Mountain View, CA

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 06 November 1994

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ICCAD '94: International Conference on Computer Aided Design

November 6 - 10, 1994

California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cao XXiao LLi JZhang RLiu SWang J(2019)A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442538:6(1109-1122)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834425
Chakrabarty KAlioto MBaas BBoon CChang MChang NChang YChang CChang SChen PChowdhury MCorsonello PElfadel IHamdioui SHashimoto MHo THomayoun HHwang YJoshi RKarnik TKermani MKim CKim TKulkarni JKursun ELarsson ELi HLi HMercier PMishra PNagata MNatarajan ANii KPande PSavidis ISeok MTan STehranipoor MTodri-Sanial AVelev MVelev MXu JZhang WZhang ZJackson S(2017)EditorialIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263857825:1(1-20)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2638578
Sheikh AEl-Maleh AElrabaa MSait S(2017)A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor RedundancyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.256953225:1(224-237)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2569532
Mirkhani SMitra SCher CAbraham JNebel WAtienza D(2015)Efficient soft error vulnerability estimation of complex designsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755776(103-108)Online publication date: 9-Mar-2015
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Garg RKhatri SWakabayashi K(2009)Efficient analytical determination of the SEU-induced pulse shapeProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509745(461-467)Online publication date: 19-Jan-2009
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Omaña MRossi DMetra C(2007)Latch Susceptibility to Transient Faults and New Hardening ApproachIEEE Transactions on Computers10.1109/TC.2007.107056:9(1255-1268)Online publication date: 1-Sep-2007
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Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects

Statistical timing and leakage power analysis of PD-SOI digital circuits

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Recommendations

Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects

Statistical timing and leakage power analysis of PD-SOI digital circuits

Fault simulation of unconventional faults in CMOS circuits

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