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Interchangeable pin routing with application to package layout

Authors:

Wayne Wei-Ming DaiAuthors Info & Claims

ICCAD '96: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Pages 668 - 673

Published: 01 January 1997 Publication History

Abstract

Many practical routing problems such as BGA, PGA, pin redistribution and test fixture routing involve routing with interchangeable pins. These routing problems, especially package layout, are becoming more difficult to do manually due to increasing speed and I/O. Currently, no commercial or university router is available for this task. In this paper, we unify these different problems as instances of the interchangeable pin routing (IPR) problem, which is NP-complete. By representing the solution space with flows in a triangulated routing network instead of grids, we developed a min-cost max-flow heuristic considering only the most important cuts in the design. The heuristic handles multiple layers, prerouted nets, and all-angle, octilinear or rectilinear wiring styles. Experiments show that the heuristic is very effective on most practical examples. It had been used to route industry designs with thousands of interchangeable pins.

References

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M.-F. Yu and W. W.-M. Dai, "Pin assignment and routing on a single-layer pin grid array," in Proc. 1st Asia and South Pacific Design Automation Conf., (Makuhari, Japan), pp. 203-208, IEEE, August 1995.

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M.-F. Yu, J. Darnauer, and W. W.-M. Dai, "Interchangeable pin routing with application to package layout," Tech. Report. UCSC-CRL-96-10, University of California, Santa Cruz, Santa Cruz, CA, April 1996.

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Cited By

Bazylevych RPałasiński MBazylevych LTaskin BHo T(2016)Topologically-Geometric RoutingProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947367(1-6)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947367
Wang KWang HDong SKoh CSze C(2013)Escape routing of mixed-pattern signals based on staggered-pin-array PCBsProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451941(93-100)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451941
Lee PLee HHo YChang YChang CLin IShen CGroeneveld PSciuto DHassoun S(2012)Obstacle-avoiding free-assignment routing for flip-chip designsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228558(1088-1093)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228558
Show More Cited By

Index Terms

Interchangeable pin routing with application to package layout
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Integrated circuits
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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cover image ACM Conferences

ICCAD '96: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

January 1997

703 pages

ISBN:0818675977

Chairmen:
Rob A. Rutenbar
Carnegie Mellon Univ., Pittsburgh, PA
,
Ralph H. J. M. Otten
Delft Univ. of Technology, Delft, The Netherlands

Copyright © Copyright (c) 1996 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
IEEE-CS: Computer Society

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IEEE Computer Society

United States

Publication History

Published: 01 January 1997

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ICCAD '96

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SIGDA
IEEE-CAS
IEEE-CS

ICCAD '96: International Conference on Computer Aided Design

November 10 - 14, 1996

California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Bazylevych RPałasiński MBazylevych LTaskin BHo T(2016)Topologically-Geometric RoutingProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947367(1-6)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947367
Wang KWang HDong SKoh CSze C(2013)Escape routing of mixed-pattern signals based on staggered-pin-array PCBsProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451941(93-100)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451941
Lee PLee HHo YChang YChang CLin IShen CGroeneveld PSciuto DHassoun S(2012)Obstacle-avoiding free-assignment routing for flip-chip designsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228558(1088-1093)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228558
Ho YLee HChang YPhillips JHu AGraeb H(2011)Escape routing for staggered-pin-array PCBsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132401(306-309)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132401
Yan TWu PMa QWong MScheffer LPhillips JHu A(2010)On the escape routing of differential pairsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133559(614-620)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133559
Yan TWong MScheffer LPhillips JHu A(2010)Recent research development in PCB layoutProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133514(398-403)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133514
Liu SChen GJing THe LDutta RHong X(2010)Effective congestion reduction for IC package substrate routingACM Transactions on Design Automation of Electronic Systems10.1145/1754405.175441215:3(1-21)Online publication date: 10-Jun-2010
https://dl.acm.org/doi/10.1145/1754405.1754412
Fang JWong MChang Y(2009)Flip-chip routing with unified area-I/O pad assignments for package-board co-designProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630002(336-339)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630002
Yan TWong M(2009)A correct network flow model for escape routingProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630001(332-335)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630001
Wang RCheng CLombardi FBhanja SMassoud YBahar R(2009)Octilinear redistributive routing in bump arraysProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531591(191-196)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531591
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