research-article

Bias temperature instability analysis of FinFET based SRAM cells

Authors:

Praveen Raghavan,

Francky CatthoorAuthors Info & Claims

DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

Article No.: 31, Pages 1 - 6

Published: 24 March 2014 Publication History

Abstract

Bias Temperature Instability (BTI) is posing a major reliability challenge for today's and future semiconductor devices as it degrades their performance. This paper provides a comprehensive BTI impact analysis, in terms of time-dependent degradation, of FinFET based SRAM cell. The evaluation metrics are read Static Noise Margin (SNM), hold SNM and Write Trip Point (WTP); while the aspects investigated include BTI impact dependence on the supply voltage, cell strength, and design styles (6 versus 8 Transistors cell). A comparison between FinFET and planar CMOS based SRAM cells degradation is also covered. The simulation performed on FinFET based cells for 10⁸ seconds of operation under nominal V_dd show that Read SNM degradation is 16.72%, which is 1.17X faster than hold SNM, while WTP improves by 6.82%. In addition, a supply voltage increment of 25% reduces the Read SNM degradation by 40%, while strengthening the cell pull-down transistors by 1.5× reduces the degradation by only 22%. Moreover, the results reveal that 8T cell degrades 1.31× faster than 6T cell, and that FinFET cells are more vulnerable (~ 2×) to BTI degradation than planar CMOS cells.

References

[1]

G. E. Moore. "Cramming more components onto integrated circuits", Electronics, Volume 38, April, 1965.

[2]

S. Hamdioui, et al., "Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes", Proc. of DATE, March, 2013, Gronoble, France.

Digital Library

[3]

S. Ramey et al., "Intrinsic Transistor Reliability Improvements from 22nm Tri-Gate Technology", Proc. of IRPS, May. 2013.

[4]

K. T. Lee et al., "Technology Scaling on High-K and Metal-Gate FinFET BTI Reliability", Proc. of IRPS, May. 2013.

[5]

S. S. Sapatnekar, et al., "Overcoming Variations in Nanometer-Scale Technologies", IEEE Transaction on emerging and selected topics in circuits and systems, Jan 2011.

[6]

W. Xiong, "Challenges Facing Embedded SRAM Scaling for the 32nm Node and Beyond", Advanced substrate news, May 14, 2008.

[7]

P. Weckx, et al., "Defect based Methodology for Workload-dependent Circuit Lifetime Projections- Application to SRAM", AProc. of IRPS, May 14, 2013.

[8]

S. Kumar, C. H. Kim, S. Sapatnekar, "Impact of NBTI on SRAM Read Stability and Design for Reliability", Pro. of ISQED, pp: 212--128, 2006.

Digital Library

[9]

K. Kang, H. Kufluoglu, K. Roy, M. A. Alam, "Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis", IEEE Trans. on CAD, Vol:26, Oct. 2005.

Digital Library

[10]

S. K. Krishnappa and H. Mahmoodi, "Comparative BTI analysis of SRAM cell designs in Nano-scale CMOS technology", Proc. of ISQED, 2011.

[11]

V. P. Hu, et al., "FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics", IEEE Transaction on Electronics Devices, March, 2011.

[12]

B. Kaczer, et al., "Atomistic Approach to Variability of Bias Temperature Instability in Circuit Simulation", Proc. of IRPS, April, 2011.

[13]

M. Alam et al., "A comprehensive model of PMOS NBTI degradation". Micro. Reliability, pp: 71--81, 2005.

[14]

S. Zafar, et al., "A comparative study of NBTI and PBTI in SiO2/HfO2 stacks with FUSI, TiN, gates". Pro. of VLSI Technology Symp., 2006.

[15]

E. Seevinck, et al., "Static-Noise Margin Analysis of MOS SRAM Cells", IEEE Journal of Solid static circuits, October, 1987.

[16]

B. S. Haran, et al "22nm technology compatible fully functional 0.1 μm² 6T-SRAM cell", Pro. of Intl. Electronic Dev. Meeting (IEDM), 2008.

[17]

Predictive Technology Model "http://ptm.asu.edu/",

[18]

M. Toledano-Luque and B. Kaczer and J. Franco and Ph. J. Roussel and T. Grasser and G. Groeseneken "Defect-centric perspective of time-dependent BTI variability", Special issue 23rd European symposium on the reliability of electron devices, failure physics and analysis, 2012.

[19]

Grasser, T. and Wagner, P. -J and Reisinger, H. and Aichinger, T. and Pobegen, G. and Nelhiebel, M. and Kaczer, B. "Defect-centric perspective of time-dependent BTI variability", Proc. of IEDM, 2011.

[20]

Kuhn, K. J. and Giles, M. D. and Becher, D. and Kolar, P. and Kornfeld, A. and Kotlyar, R. and Ma, S. T. and Maheshwari, A. and Mudanai, S. "Defect-centric perspective of time-dependent BTI variability", IEEE Transactions on Electron Devices, 2011.

[21]

Toledano-Luque, M. and Kaczer, B. and Franco, J. and Roussel, Ph.J. and Bina, M. and Grasser, T. and Cho, M. and Weckx, P. and Groeseneken, G. "Degradation of time dependent variability due to interface state generation", Proc. of VTS, 2013.

[22]

L. Zhang and R. P. Dick "Scheduled voltage scaling for increasing lifetime in the presence of NBTI", Proc. of ASP-DAC, 2009.

Digital Library

[23]

K. Agarwal and S. Nassif "Statistical Analysis of SRAM Cell Stability", Proc. of DAC, 2006.

Digital Library

[24]

M. F. Chang, et al., "A Differential Data-Aware Power-Supplied 8T SRAM CellWith Expanded Write/Read Stabilities for Lower VDDmin Applications", IEEE Journal on Solid State Circuits, June, 2010.

[25]

C. Auth et al., "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors", VLSI Tech. symp, June, 2012.

Cited By

Guo SWang RYu ZHao PRen PWang YLiao SHuang CGuo TChen AXie JHuang RParameswaran S(2017)Towards reliability-aware circuit design in nanoscale finFET technologyProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199804(780-785)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199804
Kraak DAgbo ITaouil MWeckx PCosemans SCatthoor FHamdioui SDehaene W(2017)Mitigation of sense amplifier degradation using input switchingProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130583(858-863)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130583
Agbo ITaouil MKraak DHamdioui SKukner HWeckx PRaghavan PCatthoor F(2017)Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense AmplifierIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.264361825:4(1444-1454)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2643618
Show More Cited By

Index Terms

Bias temperature instability analysis of FinFET based SRAM cells
1. Hardware

Recommendations

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI-NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage ...
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious ...
Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET
ACCT '13: Proceedings of the 2013 Third International Conference on Advanced Computing & Communication Technologies

Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short ...

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences

DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

March 2014

1959 pages

ISBN:9783981537024

General Chairs:
Gerhard Fettweis
TU Dresden, DE
,
Wolfgang Nebel
OFFIS, DE

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

In-Cooperation

SIGDA: ACM Special Interest Group on Design Automation

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 24 March 2014

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DATE '14

Sponsor:

EDAA
EDAC
The Russian Academy of Sciences

DATE '14: Design, Automation and Test in Europe

March 24 - 28, 2014

Dresden, Germany

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
174
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Guo SWang RYu ZHao PRen PWang YLiao SHuang CGuo TChen AXie JHuang RParameswaran S(2017)Towards reliability-aware circuit design in nanoscale finFET technologyProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199804(780-785)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199804
Kraak DAgbo ITaouil MWeckx PCosemans SCatthoor FHamdioui SDehaene W(2017)Mitigation of sense amplifier degradation using input switchingProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130583(858-863)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130583
Agbo ITaouil MKraak DHamdioui SKukner HWeckx PRaghavan PCatthoor F(2017)Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense AmplifierIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.264361825:4(1444-1454)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2643618
Guo SWang RYu ZHao PRen PWang YLiao SHuang CGuo TChen AXie JHuang R(2017)Towards reliability-aware circuit design in nanoscale FinFET technology: — New-generation aging model and circuit reliability simulator2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203856(780-785)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.1109/ICCAD.2017.8203856

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents