Article

FlexECC: partially relaxing ECC of MLC SSD for better cache performance

Authors:

Pradeep Subedi,

Ke ZhouAuthors Info & Claims

USENIX ATC'14: Proceedings of the 2014 USENIX conference on USENIX Annual Technical Conference

Pages 489 - 500

Published: 19 June 2014 Publication History

Abstract

The ever-growing capacity and continuously-dropping price have enabled flash-based MLC SSDs to be widely deployed as large non-volatile cache for storage systems. As MLC SSDs become increasingly denser and larger-capacity, more complex and complicated Error Correction Code (ECC) schemes are required to fight against the decreasing raw reliability associated with shrinking cells. However, sophisticated ECCs could impose excessive overhead on page decoding latency and thus hurt performance. In fact, we could avoid employing expensive ECC schemes inside SSDs which are utilized at the cache layer. We propose FlexECC, a specifically designed MLC SSD architecture for the purpose of better cache performance without compromising system reliability and consistency. With the help of an upper-layer cache manager classifying and passing down block access hints, FlexECC chooses to apply either regular ECC or lightweight Error Detection Code (EDC) for blocks. To reduce performance penalty caused by retrieving backend copies for corrupted blocks from the next-level store, FlexECC periodically schedules a scrubbing process to verify the integrity of blocks protected by EDC and replenish corrupted ones into the cache in advance. Experimental results of a proof-of-concept FlexECC implementation show that compared to SSDs armed with regular ECC schemes, FlexECC improves cache performance by up to 30.8% for representative workloads and 63.5% for read-intensive workloads due to reduced read latency and garbage collection overhead. In addition, FlexECC also retains its performance advantages even under various faulty conditions without sacrificing system resiliency.

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Kim JChoi KLee WKim J(2021)Performance Modeling and Practical Use Cases for Black-Box SSDsACM Transactions on Storage10.1145/344002217:2(1-38)Online publication date: 8-Jun-2021
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Tai AKryczka AKanaujia SJamieson KFreedman MCidon ADan TDahlia M(2019)Who's afraid of uncorrectable bit errors? online recovery of flash errors with distributed redundancyProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358891(977-991)Online publication date: 10-Jul-2019
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Published In

cover image Guide Proceedings

USENIX ATC'14: Proceedings of the 2014 USENIX conference on USENIX Annual Technical Conference

June 2014

512 pages

ISBN:9781931971102

Editors:
Garth Gibson
Carnegie Mellon University
,
Nickolai Zeldovich
Massachusetts Institute of Technology

Sponsors

VMware
NetApp
IBMR: IBM Research
Facebook: Facebook
HP: HP

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USENIX Association

United States

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Published: 19 June 2014

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Cited By

Kim JChoi KLee WKim J(2021)Performance Modeling and Practical Use Cases for Black-Box SSDsACM Transactions on Storage10.1145/344002217:2(1-38)Online publication date: 8-Jun-2021
https://dl.acm.org/doi/10.1145/3440022
Wang HZhang JHuang PYi XCheng BZhou K(2020)Cache What You Need to CacheACM Transactions on Storage10.1145/339776616:3(1-24)Online publication date: 16-Jul-2020
https://dl.acm.org/doi/10.1145/3397766
Tai AKryczka AKanaujia SJamieson KFreedman MCidon ADan TDahlia M(2019)Who's afraid of uncorrectable bit errors? online recovery of flash errors with distributed redundancyProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358891(977-991)Online publication date: 10-Jul-2019
https://dl.acm.org/doi/10.5555/3358807.3358891
Wang HYi XHuang PCheng BZhou K(2018)Efficient SSD Caching by Avoiding Unnecessary Writes using Machine LearningProceedings of the 47th International Conference on Parallel Processing10.1145/3225058.3225126(1-10)Online publication date: 13-Aug-2018
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Zhou KSun SWang HHuang PHe XLan RLi WLiu WYang T(2018)Demystifying Cache Policies for Photo Stores at ScaleProceedings of the 2018 International Conference on Supercomputing10.1145/3205289.3205299(284-294)Online publication date: 12-Jun-2018
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Kim JPark PAhn JKim JKim JKim JOskin MInoue K(2018)SSDcheckProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00044(455-468)Online publication date: 20-Oct-2018
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Wu FZhang MDu YHe XHuang PXie CWan J(2017)A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding PerformanceACM Transactions on Embedded Computing Systems10.1145/312656316:5s(1-20)Online publication date: 27-Sep-2017
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Huang SWei QFeng DChen JChen C(2016)Improving Flash-Based Disk Cache with Lazy Adaptive ReplacementACM Transactions on Storage10.1145/273783212:2(1-24)Online publication date: 26-Feb-2016
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