research-article

Compiler assisted dynamic register file in GPGPU

Authors:

Xiaoyao LiangAuthors Info & Claims

ISLPED '13: Proceedings of the 2013 International Symposium on Low Power Electronics and Design

Pages 3 - 8

Published: 04 September 2013 Publication History

Abstract

The large Register File (RF) in General Purpose Graphic Processing Units (GPGPUs) demands tremendous chip area and energy consumption. For a sustainable growth of the size of RF in future GPGPUs, emerging on-chip memory technologies such as embedded-DRAM (eDRAM) have been proposed to replace the conventional SRAM for higher density and lower leakage but with the possible penalty from the periodic refresh operations. This paper explicitly shows that the refresh penalty can be effectively mitigated by leveraging the uniqueness of GPGPU operations. A compiler assisted refresh rescheduling policy can greatly reduce the refresh overhead for maintaining the correctness of the RF operations. The proposed scheme adequately exploits the features in both architecture and compilation, and delivers comparable performance to the SRAM counterpart. At the same time, the energy savings via the removal of large SRAM leakage well compensate for the additional refresh energy. This study promotes the eDRAM-based RF as a promising alternative that enables larger capacity and better power efficiency for future GPGPUs.

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Cited By

Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu O(2018)LTRFACM SIGPLAN Notices10.1145/3296957.317321153:2(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173211
Voitsechov DZulfiqar AStephenson MGebhart MKeckler S(2018)Software-Directed Techniques for Improved GPU Register File UtilizationACM Transactions on Architecture and Code Optimization10.1145/324390515:3(1-23)Online publication date: 24-Sep-2018
https://dl.acm.org/doi/10.1145/3243905
Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu OShen XTuck JBianchini RSarkar V(2018)LTRFProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173211(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3173211
Show More Cited By

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Compiler assisted dynamic register file in GPGPU

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cover image ACM Conferences

ISLPED '13: Proceedings of the 2013 International Symposium on Low Power Electronics and Design

September 2013

440 pages

ISBN:9781479912353

General Chairs:
Pai Chou
UC Irvine / NTHU Taiwan
,
Ru Huang
Peking University
,
Program Chairs:
Yuan Xie
Penn State / AMD
,
Tanay Karnik
Intel

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IEEE Press

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Published: 04 September 2013

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ISLPED'13

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SIGDA

ISLPED'13: International Symposium on Low Power Electronics and Design

September 4 - 6, 2013

Beijing, China

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu O(2018)LTRFACM SIGPLAN Notices10.1145/3296957.317321153:2(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173211
Voitsechov DZulfiqar AStephenson MGebhart MKeckler S(2018)Software-Directed Techniques for Improved GPU Register File UtilizationACM Transactions on Architecture and Code Optimization10.1145/324390515:3(1-23)Online publication date: 24-Sep-2018
https://dl.acm.org/doi/10.1145/3243905
Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu OShen XTuck JBianchini RSarkar V(2018)LTRFProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173211(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3173211
Kloosterman JBeaumont JJamshidi DBailey JMudge TMahlke SHunter HMoreno JEmer JSanchez D(2017)ReglessProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123974(151-164)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123974
Jing NWang JFan FYu WJiang LLi CLiang XHsu WYang CLipasti MLee H(2016)Cache-emulated register fileThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195655(1-12)Online publication date: 15-Oct-2016
https://dl.acm.org/doi/10.5555/3195638.3195655
Yu LPei YChen TWu M(2016)Architecture supported register stash for GPGPUJournal of Parallel and Distributed Computing10.1016/j.jpdc.2015.12.00389:C(25-36)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1016/j.jpdc.2015.12.003
Li GChen XSun GHoffmann HLiu YWang YYang H(2015)A STT-RAM-based low-power hybrid register file for GPGPUsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744785(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744785
Cho KLee YOh YHwang GLee JXie YKarnik TKhellah MMehra R(2014)eDRAM-based tiered-reliability memory with applications to low-power frame buffersProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627626(333-338)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2627626

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