An energy-efficient 5-MHz to 20-MHz, 12-bit reconfigurable continuous-time ΣΔ modulator for 4G-LTE application
Authors: 
Jing Li, Ruiyuan Zhu, Ting Yi, Bill Liu, Zhiliang HongAuthors Info & Claims
Jing Li, Ruiyuan Zhu, Ting Yi, Bill Liu, Zhiliang HongAuthors Info & ClaimsPages 163 - 168
Abstract
This paper presents an energy-efficient reconfigurable 3rd-order continuous-time ΣΔ modulator, which can satisfy multi-band modes for 4G-LTE application. To expand the reconfigurable bandwidth range and optimize the energy efficiency, this work employs a flexible architecture, which can switch between feed-forward and feed-back topologies. At the circuit level, in order to reduce power consumption, flexibility is also introduced into all the core blocks, including amplifiers, multi-bit quantizer and feedback DAC. In addition, multi-bit quantizer utilizes interpolating technique to relax the wide-band amplifier in terms of the low power design. A power-efficient three-stage amplifier with modified positive feedback compensation is used to process high-speed signal and enhance linearity of the modulator. Implemented in 130nm CMOS technology, this work achieves peak SNR of 72.7/66.7/60.4/59.0 dB over 5/10/15/20 MHz BW with 8/14.7/16/21 mW from 1.2V supply, and the respective FOMs are optimized to 227/443/657/773 fJ/conv.
References
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Pieter Crombez, Geert Van der Plas, Michiel Steyaert, and Jan Craninckx, "A 500kHz-10MHz Multimode Power-Performance Scalable 83-to-67 dB DR CT ΣΔ in 90 nm Digital CMOS with Flexible Analog Core Circuitry", IEEE Symp. VLSI Circuits, Dig. Techn. Papers, pp. 70--71, Jun. 2009.
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Index Terms
- An energy-efficient 5-MHz to 20-MHz, 12-bit reconfigurable continuous-time ΣΔ modulator for 4G-LTE application
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Information
Published In
September 2013
440 pages
ISBN:9781479912353
- General Chairs:
- Pai Chou,
- Ru Huang,
- Program Chairs:
- Yuan Xie,
- Tanay Karnik
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IEEE Press
Publication History
Published: 04 September 2013
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- Research-article
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ISLPED'13
Sponsor:
ISLPED'13: International Symposium on Low Power Electronics and Design
September 4 - 6, 2013
Beijing, China
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Overall Acceptance Rate 398 of 1,159 submissions, 34%
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