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Alternative fetch and issue policies for the trace cache fetch mechanism

Authors:

Daniel Holmes Friendly,

Sanjay Jeram Patel,

Yale N. PattAuthors Info & Claims

MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture

Pages 24 - 33

Published: 01 December 1997 Publication History

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Abstract

The increasing widths of superscalar processors are placing greater demands upon the fetch mechanism. The trace cache meets these demands by placing logically contiguous instructions in physically contiguous storage. It is capable of supplying multiple fetch blocks each cycle. In this paper we examine two fetch and issue techniques, partial matching and inactive issue, that improve the overall performance of the trace cache by improving the effective fetch rate. We show that for the SPECint95 benchmarks partial matching increases the overall performance by 12% and inactive issue by 15%. Furthermore we apply these two techniques to issue blocks from trace segments which contain multiple execution paths. We conclude with a performance comparison between a trace cache implementing partial matching and inactive issue and an aggressive single block fetch mechanism. The trace cache increases performance by an average of 25% over the instruction cache.

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Cited By

Ramírez ALarriba-Pey JNavarro CTorrellas JValero M(2014)Software trace cacheACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667175(261-268)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667175
Ramirez AFalcon ASantana OValero M(2014)Author retrospective for software trace cacheACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2594508(45-47)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2594508
Moure JBenítez DRexachs DLuque EEgan GMuraoka Y(2006)Wide and efficient trace prediction using the local trace predictorProceedings of the 20th annual international conference on Supercomputing10.1145/1183401.1183411(55-65)Online publication date: 28-Jun-2006
https://dl.acm.org/doi/10.1145/1183401.1183411
Show More Cited By

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Alternative fetch and issue policies for the trace cache fetch mechanism

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Published In

cover image ACM Conferences

MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture

December 1997

369 pages

ISBN:0818679778

Chairmen:
Mark Smotherman
Clemson Univ., Clemson, SC
,
Tom Conte
North Carolina State Univ., Raleigh

Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE-CS\TCMM: TC on Microprocessors & Microcomputers

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IEEE Computer Society

United States

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Published: 01 December 1997

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MICRO97

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MICRO97: 30th Annual International Symposium on Microarchitecture

December 1 - 3, 1997

North Carolina, Research Triangle Park, USA

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MICRO 30 Paper Acceptance Rate 35 of 103 submissions, 34%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

Ramírez ALarriba-Pey JNavarro CTorrellas JValero M(2014)Software trace cacheACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667175(261-268)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667175
Ramirez AFalcon ASantana OValero M(2014)Author retrospective for software trace cacheACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2594508(45-47)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2594508
Moure JBenítez DRexachs DLuque EEgan GMuraoka Y(2006)Wide and efficient trace prediction using the local trace predictorProceedings of the 20th annual international conference on Supercomputing10.1145/1183401.1183411(55-65)Online publication date: 28-Jun-2006
https://dl.acm.org/doi/10.1145/1183401.1183411
Cher CPark IVijayKumar T(2006)Do trace cache, value prediction and prefetching improve SMT throughput?Proceedings of the 19th international conference on Architecture of Computing Systems10.1007/11682127_17(232-251)Online publication date: 13-Mar-2006
https://dl.acm.org/doi/10.1007/11682127_17
Zmily AKozyrakis CRoy KTiwari V(2005)Energy-efficient and high-performance instruction fetch using a block-aware ISAProceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077614(36-41)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077614
Ramirez ALarriba-Pey JValero M(2005)Software Trace CacheIEEE Transactions on Computers10.1109/TC.2005.1354:1(22-35)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1109/TC.2005.13
Zmily AKillian EKozyrakis C(2005)Improving instruction delivery with a block-aware ISAProceedings of the 11th international Euro-Par conference on Parallel Processing10.1007/11549468_60(530-539)Online publication date: 30-Aug-2005
https://dl.acm.org/doi/10.1007/11549468_60
Seznec AFraboulet A(2003)Effective ahead pipelining of instruction block address generationACM SIGARCH Computer Architecture News10.1145/871656.85964631:2(241-252)Online publication date: 1-May-2003
https://dl.acm.org/doi/10.1145/871656.859646
Seznec AFraboulet AGottlieb ALi K(2003)Effective ahead pipelining of instruction block address generationProceedings of the 30th annual international symposium on Computer architecture10.1145/859618.859646(241-252)Online publication date: 9-Jun-2003
https://dl.acm.org/doi/10.1145/859618.859646
Rosner RMoffie MSazeides YRonen RBanerjee UGallivan KGonzalez A(2003)Selecting long atomic traces for high coverageProceedings of the 17th annual international conference on Supercomputing10.1145/782814.782818(2-11)Online publication date: 23-Jun-2003
https://dl.acm.org/doi/10.1145/782814.782818
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