research-article

Power-efficient accelerator allocation in adaptive dark silicon many-core systems

Authors:

Muhammad Usman Karim Khan,

Muhammad Shafique,

Jörg HenkelAuthors Info & Claims

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

Pages 916 - 919

Published: 09 March 2015 Publication History

Abstract

Modern many-core systems in the dark silicon era face the predicament of underutilized resources of the chip due to power constraints. Therefore, hardware accelerators are becoming popular as they can overcome this problem by exercising a part of the program on dedicated custom logic in an energy efficient way. However, efficient accelerator usage poses numerous challenges, like adaptations for accelerator's sharing schedule on the many-core systems under run-time varying scenarios. In this work, we propose a power-efficient accelerator allocation scheme for adaptive many-core systems that maximally utilizes and dynamically allocates a shared accelerator to competing cores, such that deadlines of the executing applications are met and the total power consumption of the overall system is minimized. The experimental results demonstrate power minimization and high accelerator utilization for a many-core system.

References

[1]

R. H. Dennard et al., "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," in IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256--268, 1974.

[2]

H. Esmaeilzadeh, E. Blem, R. S. Amant, K. Sankaralingam, D. Burger, "Dark silicon and the end of multicore scaling," in International Symposium on Computer Architecture (ISCA), pp. 365--376, 2011.

Digital Library

[3]

M. Shafique, S. Garg, J. Henkel, D. Marculescu, "The EDA Challenges in the Dark Silicon Era," in Design Automation Conference (DAC), 2014.

Digital Library

[4]

L. Seiler et al., "Larrabee: A Many-Core x86 Architecture for Visual Computing," in IEEE MICRO, pp. 10--21, 2009.

Digital Library

[5]

M. Mattina, "Architecture and Performance of the Tile-GX Processor Family," white paper, pp. 1--18, 2014.

[6]

M. Shafique, L. Bauer, J. Henkel, "Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms," in Journal of Signal Processing Systems (JSPS), vol. 60, issue 2, pp. 183--210, 2010.

Digital Library

[7]

C. Liu, O. Granados, R. Duarte, J. Andrian, "Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components," in Journal of Information Processing Systems, vol. 8, no. 1, pp. 133--144, 2012.

[8]

Altera, "Nios II Custom Instruction User Guide," 2011.

[9]

M. U. K. Khan, M. Shafique, J. Henkel, "Hardware-Software Collaborative Complexity Reduction Scheme for the Emerging HEVC Intra Encoder," in Design, Automation and Test in Europe (DATE), pp. 125--128, 2013.

Digital Library

[10]

H. Shojania, L. Baochun, "Parallelized Progressive Network Coding with Hardware Acceleration," in IEEE International Workshop on Quality of Service, pp. 47--55, 2007.

[11]

D. Sheldon, A. Forin, "An Online Scheduler for Hardware Accelerators on General Purpose Operating Systems," Tech. report, Microsoft Research, 2010.

[12]

C. Huang, D. Sheldon, F. Vahid, "Dynamic Tuning of Configurable Architectures: the AWW Online Algorithm," in International Conference on Hardware/Software Codesign and System Synthesis, pp. 97--102, 2008.

Digital Library

[13]

T. Majumder, P. P. Pande, A. Kalyanaraman, "High-throughput, Energy-Efficient Network-on-Chip-Based Hardware Accelerators," in Journal of Sustainable Computing: Informatics and Systems, vol. 3, issue 1, pp. 36--46, 2013.

[14]

J. Cong, M. A. Ghodrat, M. Gill, B. Grigorian, G. Reinman, "Architecture support for accelerator-rich CMPs," in Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012.

Digital Library

[15]

E. Cota, P. Mantovani, M. Petracca, M. Casu, and L. Carloni, "Accelerator Memory Reuse in the Dark Silicon Era," in IEEE Computer Architecture Letters, pp. 1--4, 2012.

[16]

J. A. Clemente, I. V. Beretta, V. Rana, D. Atienza, D. Sciuto, "A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platform," in ACM Transactions on Reconfigurable Technology and Systems, vol. 7, no. 2, 2014.

Digital Library

[17]

S. Paul, R. Karam, S. Bhunia, R. Puri, "Energy-Efficient Hardware Acceleration through Computing in the Memory," in Design, Automation and Test in Europe (DATE), 2014.

Digital Library

[18]

J. A. Nelder, R. Mead, "A Simplex Method for Function Minimization," in The Computer Journal, vol. 7, no. 4, 1965.

[19]

T. E. Carlson, W. Heirman, L. Eeckhout, "Sniper: Exploring the Level of Abstraction for Scalable and Accurate Multi-core Simulation," in SC, pp. 1--12, 2011.

Digital Library

[20]

S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, N. P. Jouppi, "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures," in MICRO, pp. 469--480, 2009.

Digital Library

Cited By

Khan MShafique MGupta ASchumann THenkel JFanucci LTeich J(2016)Power-efficient load-balancing on heterogeneous computing platformsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972150(1469-1472)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972150
Shafique MHenkel JMarculescu DLiu F(2015)Mitigating the Power Density and Temperature Problems in the Nano-EraProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840845(176-177)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840845
Henkel JBukhari HGarg SKhan MKhdr HKriebel FOgras UParameswaran SShafique MIvanov AMarculescu DPande PFlich JPattabiraman K(2015)Dark SiliconProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2788707(1-8)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2786572.2788707

Index Terms

Power-efficient accelerator allocation in adaptive dark silicon many-core systems

Recommendations

Out-of-core implementation for accelerator kernels on heterogeneous clouds

Cloud environments today are increasingly featuring hybrid nodes containing multicore CPU processors and a diverse mix of accelerators such as Graphics Processing Units (GPUs), Intel Xeon Phi co-processors, and Field-Programmable Gate Arrays (FPGAs) to ...
Vectorizing Unstructured Mesh Computations for Many-core Architectures
PMAM'14: Proceedings of Programming Models and Applications on Multicores and Manycores

Achieving optimal performance on the latest multi-core and many-core architectures depends more and more on making efficient use of the hardware's vector processing capabilities. While auto-vectorizing compilers do not require the use of vector ...
Vectorizing Unstructured Mesh Computations for Many-core Architectures
PMAM'14: Proceedings of Programming Models and Applications on Multicores and Manycores

Achieving optimal performance on the latest multi-core and many-core architectures depends more and more on making efficient use of the hardware's vector processing capabilities. While auto-vectorizing compilers do not require the use of vector ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

March 2015

1827 pages

ISBN:9783981537048

General Chair:
Wolfgang Nebel
OFFIS & University of Oldenburg, DE
,
Program Chair:
David Atienza
EPFL, CH

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
Russian Acadamy of Sciences: Russian Acadamy of Sciences
IEEE Council on Electronic Design Automation (CEDA)

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 09 March 2015

Check for updates

Qualifiers

Research-article

Conference

DATE '15

Sponsor:

EDAA
EDAC
SIGDA
Russian Acadamy of Sciences

DATE '15: Design, Automation and Test in Europe

March 9 - 13, 2015

Grenoble, France

Acceptance Rates

DATE '15 Paper Acceptance Rate 206 of 915 submissions, 23%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
130
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)0

Reflects downloads up to 01 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Khan MShafique MGupta ASchumann THenkel JFanucci LTeich J(2016)Power-efficient load-balancing on heterogeneous computing platformsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972150(1469-1472)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972150
Shafique MHenkel JMarculescu DLiu F(2015)Mitigating the Power Density and Temperature Problems in the Nano-EraProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840845(176-177)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840845
Henkel JBukhari HGarg SKhan MKhdr HKriebel FOgras UParameswaran SShafique MIvanov AMarculescu DPande PFlich JPattabiraman K(2015)Dark SiliconProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2788707(1-8)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2786572.2788707

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents