Clustering based simulated annealing for standard cell placement

Simulated annealing has been shown to be effective in producing good quality results for the standard cell placement problem. Its main drawback is the excessive computation time required, which increases significantly with the problem size. In this paper we present a novel technique for reducing the effective problem size for simulated annealing without compromising the solution quality. We form clusters of cells based on their interconnections, and place them first using conventional simulated annealing. We then break up the clusters, and place the individual cells using another simulated annealing process that does a refinement on the placement. The original problem is thus divided into two subproblems, each requiring much less time. The results with this 2-stage simulated annealing have been superior to those with our conventional simulated annealing implementation, with more significant improvements observed for larger chips. For chips with more than 2500 cells, we have observed a factor of 2 to 3 speed-up in CPU time, together with a 6 to 17% improvement in the estimated wire-length.