research-article

Runtime power limiting of parallel applications on Intel Xeon Phi processors

Authors:

Vaibhav Sundriyal,

Masha Sosonkina,

Yuzhong ShenAuthors Info & Claims

E2SC '16: Proceedings of the 4th International Workshop on Energy Efficient Supercomputing

Pages 39 - 45

Published: 13 November 2016 Publication History

Abstract

Energy-efficient computing is crucial to achieving exascale performance. Power capping and dynamic voltage/frequency scaling may be used to achieve energy savings. The Intel Xeon Phi implements a power capping strategy, where power thresholds are employed to dynamically set voltage/frequency at the runtime. By default, these power limits are much higher than the majority of applications would reach. Hence, this work aims to set the power limits according to the workload characteristics and application performance. Certain models, originally developed for the CPU performance and power, have been adapted here to determine power-limit thresholds in the Xeon Phi. Next, a procedure to select these thresholds dynamically is proposed, and its limitations outlined. When this runtime procedure along with static power-threshold assignment were compared with the default execution, energy savings ranging from 5% to 49% were observed, mostly for memory-intensive applications.

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Cited By

Wang JHe XLawson GSosonkina MEzer TShen Y(2020)Applying EMD/HHT analysis to power traces of applications executed on systems with Intel Xeon PhiInternational Journal of High Performance Computing Applications10.1177/109434201773161234:2(187-198)Online publication date: 17-Jun-2020
https://dl.acm.org/doi/10.1177/1094342017731612
Lawson GSosonkina MEzer TShen Y(2017)Empirical Mode Decomposition for Modeling of Parallel Applications on Intel Xeon Phi ProcessorsProceedings of the 17th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing10.1109/CCGRID.2017.99(1000-1008)Online publication date: 14-May-2017
https://dl.acm.org/doi/10.1109/CCGRID.2017.99

Runtime power limiting of parallel applications on Intel Xeon Phi processors

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Information & Contributors

Information

Published In

cover image ACM Conferences

E2SC '16: Proceedings of the 4th International Workshop on Energy Efficient Supercomputing

November 2016

91 pages

ISBN:9781509038565

General Chairs:
Kirk Cameron
Virginia Tech
,
Adolfy Hoisie
PNNL
,
Darren Kerbyson
PNNL
,
David Lowenthal
ASU
,
Dimitrios S. Nikolopoulos
Queen's University of Belfast, UK
,
Sudha Yalamanchili
Georgia Institute of Technology
,
Program Chairs:
Kevin Barker
PNNL
,
Rong Ge
Clemson University

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SIGHPC: ACM Special Interest Group on High Performance Computing, Special Interest Group on High Performance Computing
IEEE-CS\DATC: IEEE Computer Society

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SIGARCH: ACM Special Interest Group on Computer Architecture

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IEEE Press

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Published: 13 November 2016

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SC16

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SC16: The International Conference for High Performance Computing, Networking, Storage and Analysis

November 13 - 18, 2016

Utah, Salt Lake City

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Overall Acceptance Rate 17 of 33 submissions, 52%

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Cited By

Wang JHe XLawson GSosonkina MEzer TShen Y(2020)Applying EMD/HHT analysis to power traces of applications executed on systems with Intel Xeon PhiInternational Journal of High Performance Computing Applications10.1177/109434201773161234:2(187-198)Online publication date: 17-Jun-2020
https://dl.acm.org/doi/10.1177/1094342017731612
Lawson GSosonkina MEzer TShen Y(2017)Empirical Mode Decomposition for Modeling of Parallel Applications on Intel Xeon Phi ProcessorsProceedings of the 17th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing10.1109/CCGRID.2017.99(1000-1008)Online publication date: 14-May-2017
https://dl.acm.org/doi/10.1109/CCGRID.2017.99

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