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CRIS: a test cultivation program for sequential VLSI circuits

Authors:

Daniel G. Saab,

Youssef G. Saab,

Jacob A. AbrahamAuthors Info & Claims

ICCAD '92: Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Pages 216 - 219

Published: 08 November 1992 Publication History

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References

[1]

H-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovani-Vicentelli, "Test Generation for Sequential Circuits," IEEE, Transactions on Computer Aided- Design., vol. CAD-7, pp. 1081-1093, Oct. 1988.

Google Scholar

[2]

T.M. Niermann and J. H. Patel, "H1TEC: A Test Generation Package for Sequential Circuits," European Design Automation Conference, pp. 214-218, 1991.

Digital Library

Google Scholar

[3]

W.-T. Cheng, "The BACK Algorithm for Sequential Test Generation," International Conference on Computer Aided Design, pp. 214-218, 1991.

Google Scholar

[4]

Miron Abramovici, Melvin A. Breuer, and Arthur D. Friedman, Digital Systems Testing and Testable Design. NewYork: Computer Science Press, 1990.

Google Scholar

[5]

J. Galiay et al., "Physical Versus Logic Fault Models in MOS LSI Circuits, Impact on their Testability," Int. Syrup. Fault Tolerant Computing, pp. 195-202, 1979.

Google Scholar

[6]

R.L. Wadsack, "Fault Modeling and Simulation of CMOS and MOS Integrated Circuits," The Bell System Tech. Journal, pp. 1449-1474, June 1978.

Google Scholar

[7]

Y.M. E1-Ziq, "Automatic Test Generation for Stuck- Open Faults in CMOS VLSI," Design Automation Conference, pp. 347-352, June 1981.

Digital Library

Google Scholar

[8]

M.K. Reddy, S. M. Reddy, and P. Agrawal, "Transistor Level Test Generation for MOS Circuits," Design Automation Conference, pp. 825-828, 1985.

Digital Library

Google Scholar

[9]

S. Seshu and D. N. Freeman, "The diagnosis of asynchronous sequential switching systems," IRE Transactions on Electronic Computing, vol. EC-11, pp. 459-465, August 1962.

Google Scholar

[10]

K.-T. Cheng and V. D. Agrawal, Unified Methods for VLSI Simulation and Test Generation. Boston, MA: Kluwer Academic Publishers, 1989.

Digital Library

Google Scholar

[11]

D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning. Massachusetts: Addison-Wesley, 1989.

Digital Library

Google Scholar

[12]

F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," in Proceedings of the 1989 Int. Syrup. on Circuits and Systems, Portland, Oregon, May 1989.

Google Scholar

[13]

J.P. Cohoon and W. D. Paris, "Genetic Placement," in Proc. of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 422-425, November 1986.

Google Scholar

[14]

F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. of the Int. Test Conf., pp. 785-794, 1985.

Google Scholar

Cited By

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Pomeranz IReddy SWakabayashi K(2009)Dynamic test compaction for a random test generation procedure with input cube avoidanceProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509786(672-677)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509786
Pomeranz IReddy SLauwereins RMadsen J(2007)On test generation by input cube avoidanceProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266478(522-527)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266478
Sheng SHsiao M(2002)Efficient Sequential Test Generation Based on Logic SimulationIEEE Design & Test10.1109/MDT.2002.103379319:5(56-64)Online publication date: 1-Sep-2002
https://dl.acm.org/doi/10.1109/MDT.2002.1033793
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Index Terms

CRIS: a test cultivation program for sequential VLSI circuits
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Robustness
    1. Hardware reliability

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ICCAD '92: Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

November 1992

637 pages

ISBN:0897915402

Chairmen:
Louise Trevillyan
IBM Corp., Yorktown Heights, NY
,
Michael Lightner
Univ. of Colorado, Boulder

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IEEE Computer Society Press

Washington, DC, United States

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Published: 08 November 1992

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Pomeranz IReddy SWakabayashi K(2009)Dynamic test compaction for a random test generation procedure with input cube avoidanceProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509786(672-677)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509786
Pomeranz IReddy SLauwereins RMadsen J(2007)On test generation by input cube avoidanceProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266478(522-527)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266478
Sheng SHsiao M(2002)Efficient Sequential Test Generation Based on Logic SimulationIEEE Design & Test10.1109/MDT.2002.103379319:5(56-64)Online publication date: 1-Sep-2002
https://dl.acm.org/doi/10.1109/MDT.2002.1033793
Hamzaoglu IPatel JSentovich E(2000)Deterministic test pattern generation techniques for sequential circuitsProceedings of the 2000 IEEE/ACM international conference on Computer-aided design10.5555/602902.603023(538-543)Online publication date: 5-Nov-2000
https://dl.acm.org/doi/10.5555/602902.603023
Pomeranz IReddy S(2000)Procedures for Static Compaction of Test Sequences for Synchronous Sequential CircuitsIEEE Transactions on Computers10.1109/12.86221949:6(596-607)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1109/12.862219
Lin XPomeranz IReddy SWhite JSentovich E(1999)Techniques for improving the efficiency of sequential circuit test generationProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.339608(147-151)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.339608
Guo RReddy SPomeranz I(1999)ProptestProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.310019(653-659)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.310019
Pomeranz IReddy S(1999)A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n$n$-Detections in Combinational CircuitsIEEE Transactions on Computers10.1109/12.80516448:10(1145-1152)Online publication date: 1-Oct-1999
https://dl.acm.org/doi/10.1109/12.805164
Becker BKeim MKrieger R(1999)Hybrid Fault Simulation for Synchronous Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:100837652245115:3(219-238)Online publication date: 1-Dec-1999
https://dl.acm.org/doi/10.1023/A%3A1008376522451
Nguyen HRoy RChatterjee A(1999)Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:100836630469914:3(259-272)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1023/A%3A1008366304699
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Optimized reversible binary-coded decimal adders

Hardware Designs for Decimal Floating-Point Addition and Related Operations

Logic Networks of Carry-Save Adders

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