Article

Modeling universal instruction selection

Authors:

Gabriel Hjort Blindell,

Roberto Castañeda Lozano,

Christian SchulteAuthors Info & Claims

CP'15: Proceedings of the 21st International Conference on Principles and Practice of Constraint Programming

Pages 609 - 626

Published: 31 August 2015 Publication History

Abstract

Instruction selection implements a program under compilation by selecting processor instructions and has tremendous impact on the performance of the code generated by a compiler. This paper introduces a graph-based universal representation that unifies data and control flow for both programs and processor instructions. The representation is the essential prerequisite for a constraint model for instruction selection introduced in this paper. The model is demonstrated to be expressive in that it supports many processor features that are out of reach of state-of-the-art approaches, such as advanced branching instructions, multiple register banks, and SIMD instructions. The resulting model can be solved for small to medium size input programs and sophisticated processor instructions and is competitive with LLVM in code quality. Model and representation are significant due to their expressiveness and their potential to be combined with models for other code generation tasks.

References

[1]

Opturion CPX user's guide: Version 1.0.2. Tech. rep., Opturion Pty Ltd (2013)

[2]

Aho, A.V., Ganapathi, M., Tjiang, S.W.K.: Code Generation Using Tree Matching and Dynamic Programming. Transactions on Programming Languages and Systems 11(4), 491-516 (1989)

[3]

Allen, J.R., Kennedy, K., Porterfield, C., Warren, J.: Conversion of Control Dependence to Data Dependence. In: ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages, pp. 177-189 (1983)

[4]

Arslan, M.A., Kuchcinski, K.: Instruction Selection and Scheduling for DSP Kernels on Custom Architectures. In: EUROMICRO Conference on Digital System Design (2013)

[5]

Barany, G., Krall, A.: Optimal and Heuristic Global Code Motion for Minimal Spilling. In: Jhala, R., De Bosschere, K. (eds.) Compiler Construction. LNCS, vol. 7791, pp. 21-40. Springer, Heidelberg (2013)

[6]

Bashford, S., Leupers, R.: Constraint Driven Code Selection for Fixed-Point DSPs. In: ACM/IEEE Design Automation Conference, pp. 817-822 (1999)

[7]

Bednarski, A., Kessler, C.W.: Optimal Integrated VLIW Code Generation with Integer Linear Programming. In: Nagel, W.E., Walter, W.V., Lehner, W. (eds.) Euro-Par 2006. LNCS, vol. 4128, pp. 461-472. Springer, Heidelberg (2006)

[8]

Bruno, J., Sethi, R.: Code Generation for a One-Register Machine. Journal of the ACM 23(3), 502-510 (1976)

[9]

Buchwald, S., Zwinkau, A.: Instruction Selection by Graph Transformation. In: International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pp. 31-40 (2010)

[10]

Castañeda Lozano, R., Carlsson, M., Blindell, G.H., Schulte, C.: Combinatorial spill code optimization and ultimate coalescing. In: Kulkarni, P. (ed.) Languages, Compilers, Tools and Theory for Embedded Systems, pp. 23-32. ACM Press, Edinburgh, UK (2014)

[11]

Lozano, R.C., Carlsson, M., Drejhammar, F., Schulte, C.: Constraint-Based Register Allocation and Instruction Scheduling. In: Milano, M. (ed.) CP 2012. LNCS, vol. 7514, pp. 750-766. Springer, Heidelberg (2012)

[12]

Click, C.: Global Code Motion/Global Value Numbering. In: ACM SIGPLAN 1995 Conference on Programming Language Design and Implementation, pp. 246-257 (1995)

[13]

Cordella, L.P., Foggia, P., Sansone, C., Vento, M.: A (Sub)Graph Isomorphism Algorithm for Matching Large Graphs. IEEE Transactions on Pattern Analysis and Machine Intelligence 26(10), 1367-1372 (2004)

[14]

Cytron, R., Ferrante, J., Rosen, B.K., Wegman, M.N., Zadeck, F.K.: Efficiently Computing Static Single Assignment Form and the Control Dependence Graph. ACM TOPLAS 13(4), 451-490 (1991)

[15]

Ebner, D., Brandner, F., Scholz, B., Krall, A., Wiedermann, P., Kadlec, A.: Generalized Instruction Selection Using SSA-Graphs. In: ACM SIGPLAN-SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, pp. 31-40 (2008)

[16]

Eckstein, E., König, O., Scholz, B.: Code Instruction Selection Based on SSA-Graphs. In: Anshelevich, E. (ed.) SCOPES 2003. LNCS, vol. 2826, pp. 49-65. Springer, Heidelberg (2003)

[17]

Ertl, M.A.: Optimal Code Selection in DAGs. In: ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pp. 242-249 (1999)

[18]

Ertl, M.A., Casey, K., Gregg, D.: Fast and Flexible Instruction Selection with On-Demand Tree-Parsing Automata. In: ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 52-60 (2006)

[19]

Floch, A., Wolinski, C., Kuchcinski, K.: Combined Scheduling and Instruction Selection for Processors with Reconfigurable Cell Fabric. In: International Conference on Application-Specific Systems, Architectures and Processors, pp. 167-174 (2010)

[20]

Garey, M., Johnson, D.: Computers and Intractability: A Guide to the Theory of NP-Completeness. Freeman (1979)

[21]

Gebotys, C.H.: An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy. In: International Symposium on System Synthesis, pp. 41-47 (1997)

[22]

Glanville, R.S., Graham, S.L.: A New Method for Compiler Code Generation. In: ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages, pp. 231-254 (1978)

[23]

Hjort Blindell, G.: Survey on Instruction Selection: An Extensive and Modern Literature Study. Tech. Rep. KTH/ICT/ECS/R-13/17-SE, KTH Royal Institute of Technology, Sweden (October 2013)

[24]

Johnson, N., Mycroft, A.: Combined Code Motion and Register Allocation Using the Value State Dependence Graph. In: International Conference of Compiler Construction, pp. 1-16 (2003)

[25]

Koes, D.R., Goldstein, S.C.: Near-Optimal Instruction Selection on DAGs. In: IEEE/ACM International Symposium on Code Generation and Optimization, pp. 45-54 (2008)

[26]

Lattner, C., Adve, V.: LLVM: A compilation framework for lifelong program analysis & transformation. In: IEEE/ACM International Symposium on Code Generation and Optimization (2004)

[27]

Laurière, J.L.: A Language and a Program for Stating and Solving Combinatorial Problems. Artificial Intelligence 10(1), 29-127 (1978)

[28]

Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. In: IEEE MICRO-30, pp. 330-335 (1997)

[29]

Leupers, R.: Code Selection for Media Processors with SIMD Instructions. In: Conference on Design, Automation and Test in Europe, pp. 4-8 (2000)

[30]

Martin, K., Wolinski, C., Kuchcinski, K., Floch, A., Charot, F.: Constraint-Driven Instructions Selection and Application Scheduling in the DURASE System. In: International Conference on Application-Specific Systems, Architectures and Processors, pp. 145-152 (2009)

[31]

Nethercote, N., Stuckey, P.J., Becket, R., Brand, S., Duck, G.J., Tack, G.R.: MiniZinc: Towards a Standard CP Modelling Language. In: Bessière, C. (ed.) CP 2007. LNCS, vol. 4741, pp. 529-543. Springer, Heidelberg (2007)

[32]

Pelegrí-Llopart, E., Graham, S.L.: Optimal Code Generation for Expression Trees: An Application of BURS Theory. In: ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pp. 294-308 (1988)

[33]

Sweetman, D.: See MIPS Run, Second Edition. Morgan Kaufmann (2006)

[34]

Tanaka, H., Kobayashi, S., Takeuchi, Y., Sakanushi, K., Imai, M.: A Code Selection Method for SIMD Processors with PACK Instructions. In: International Workshop on Software and Compilers for Embedded Systems, pp. 66-80

[35]

Živojnovič, V., Martínez Velarde, J., Schläger, C., Meyr, H.: DSPstone: A DSP-Oriented Benchmarking Methodology. In: Conference on Signal Processing Applications and Technology, pp. 715-720 (1994)

[36]

Wilson, T., Grewal, G., Halley, B., Banerji, D.: An Integrated Approach to Retargetable Code Generation. In: International Symposium on High-Level Synthesis, pp. 70-75 (1994)

Cited By

Hoffmann RMcCreesh CReilly CSingh SMarkovitch S(2017)Between subgraph isomorphism and maximum common subgraphProceedings of the Thirty-First AAAI Conference on Artificial Intelligence10.5555/3298023.3298136(3907-3914)Online publication date: 4-Feb-2017
https://dl.acm.org/doi/10.5555/3298023.3298136
Blindell GCarlsson MLozano RSchulte C(2017)Complete and Practical Universal Instruction SelectionACM Transactions on Embedded Computing Systems10.1145/312652816:5s(1-18)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126528

Index Terms

Modeling universal instruction selection
1. Software and its engineering
  1. Software notations and tools
    1. Compilers

Index terms have been assigned to the content through auto-classification.

Recommendations

Automatic custom instruction identification for application-specific instruction set processors

The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom ...
Selection of instruction set extensions for an FPGA embedded processor core
IPDPS'06: Proceedings of the 20th international conference on Parallel and distributed processing

A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional ...
Increasing the instruction fetch rate via block-structured instruction set architectures
MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture

To exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance ...

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings

CP'15: Proceedings of the 21st International Conference on Principles and Practice of Constraint Programming

August 2015

719 pages

ISBN:9783319232188

Editor:
Gilles Pesant
École Polytechnique de Montréal, Montréal, Canada

Sponsors

SFI: Science Foundation Ireland
Springer
ECCAI123: European Coordinating Committee for Artificial Intelligence
Association for Constraint Programming
The Association for Logic Programming: The Association for Logic Programming

Publisher

Springer

Gewerbestrasse 11 CH-6330, Cham (ZG), Switzerland

Publication History

Published: 31 August 2015

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 18 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Hoffmann RMcCreesh CReilly CSingh SMarkovitch S(2017)Between subgraph isomorphism and maximum common subgraphProceedings of the Thirty-First AAAI Conference on Artificial Intelligence10.5555/3298023.3298136(3907-3914)Online publication date: 4-Feb-2017
https://dl.acm.org/doi/10.5555/3298023.3298136
Blindell GCarlsson MLozano RSchulte C(2017)Complete and Practical Universal Instruction SelectionACM Transactions on Embedded Computing Systems10.1145/312652816:5s(1-18)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126528

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents