Tutorial on parallel processing for design automation applications (tutorial session)
Abstract
This tutorial is designed as an introduction to the field of parallel processing and to its impact on the field of design automation (DA). It starts by reviewing the history of parallel processing. Examples of current hardware are discussed, focusing on the trade offs between custom hardware and general purpose hardware. Interconnection of processors and memory is discussed to demonstrate the range of architectural options available. Then, two key DA algorithms, implemented on parallel machines, are analyzed. Finally, there is a list of other DA applications that have already been implemented on parallel hardware and a list of future candidates for parallel processing. The tutorial concludes with a summary of future needs and directions. High on this list is the need for program design aids and new compilers.
References
[1]
S. Fernbach, "Parallelism in Computing," Proc. of International Conference on Parallel Processing (ICPP), August, 1981, pp. 1-4.
[2]
R. A. Stokes, "Burroughs Scientific Processor," High Speed Computer and Algorithm Organization, pp. 85-89, 1977.
[3]
R. M. Russell, "The CRAY-I Computer Systems," Comm. ACM, pp. 63-72, January, 1978.
[4]
R. J. Swan, S. H. Fuller, and D. P. Siewiorek, "CM*-A Modular, Multi-Microprocessor," Proc. of National Computer Conference (NCC), 1977, pp. 645-655.
[5]
S. Renben and P. C. Patton, "BCA: A Bus Connected Architecture," Proc. of ICPP, St. Charles, III., August, 1985, pp. 79-88.
[6]
C. Maples, "Pyramids, Crossbars and Thousands of Processors," Proc. of ICPP, St. Charles, III., August, 1985, pp. 681-688.
[7]
H. G. Adshead, '~Towards VLSI Complexity: The DA Algorithm Scaling Problem: Can Special DA Hardware Help?," Proc. of 19th Design Automation Conference (DAC), Las Vegas, Nev., June, 1982, pp. 339-344.
[8]
T. Blank, "A Survey of Hardware Accelerators Used in Computer-Aided Design," IEEE Design & Test, pp. 21-39, August, 1984.
[9]
G. F. Pfister, "The Yorktown Simulation Engine: Introduction," Proc. of 19th DAC, Las Vegas, Nev., June, 1982, pp. 51-54.
[10]
M. M. Denneau, "The Yorktown Simulation Engine," Proc. of 19th DAC, Las Vegas, Nev., June, 1982, pp. 55-59.
[11]
M. Abramovici, Y. H. Levendel, and P. R. Menon, "A Logic Simulation Machine," Proc. of 19th DAC, Las Vegas, Nev., June, 1982, pp. 60-64.
[12]
T. Sasaki, N. Koike, K. Ohmori, and K. Tomita, "HAL: A Block Level Hardware Logic Simulator," Proc. of 20th DAC, Miami Beach, Fla., June, 198:3, pp. 150-156.
[13]
N. Van Brunt, "The ZYCAD Logic Eva luator and its Application to Modern System Design," Proc. of }{EEE Internationa} Conference on Computer Desi:gn: VLSI in Computers (ICCD), Port Chester, N.Y., October, 1983, pp. 232-233.
[14]
M. E. Glazier and A. P. Ambler, "ULTIMATE: A Hardware Logic Simulation Engine," Proc. of 21st, DAC, Albuquerque, N.M., June, 1984, pp. 336-342.
[15]
N. Koike and K. Ohmori, "MAN-YO: A Special Purpose Parallel Machine for Logic Design Automation," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 583-590.
[16]
C. E. Leiser:~on, "Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 393-402.
[17]
Y-C. Hong, T. H. Payne, and Le B. O. Ferguson, "An Architecture for a Dataflow Multiprocessor," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 349-355.
[18]
W. G. Paseman, "Applying Data Flow in the Rea~ World," BYTE Magazine, May, 1985.
[19]
C. L. Seitz, "The Cosmic Cube," Comm. ACM, vol. 28, January, 1985, pp. 22-33.
[20]
E. Datum, H. Gethoffer, and K. Kaiser, "Hardware Support for Automatic Wiring," Proc. of 19th DAC, Las Vegas, Nev., June, 1982, pp. 219-223.
[21]
R. Nair, S. J. Hong, S. Liles, and R. Villani, "Global Wiring on a Wire Routing Machine," Proc. of 19th DAC, Las Vegas, Nev., June, 1982, pp. 224-231.
[22]
L. Seiler, "A Hardware Assisted Design Rule Check Architecture," Proc. of 19th DAC, Las Vegas, Nev., June, 1982, pp. 232-238.
[23]
F. Gregoretti and Z. Segall, "Analysis and Evaluation of VLSI Design Rule Checking Implementation in a Multiprocessor," Proc. of ICPP, Bellaire, Mich., August, 1984, pp. 7-14.
[24]
C. P. Arnold, M. I. Parr, and M. B. Dewe, "An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations," IEEE Tran. on Computers, vol. C-32, pp. 265-272, March, 1983.
[25]
Z. Barzilai, L. Huisman, G. Silberman, D. Tang, and L. Woo, "Simulating Pass Transistor Circuits using Logic Simulation Machines," Proc. of 20th DAC, Miami Beach, Fla., June, 1983, pp. 157-163.
[26]
J. T. Deutsch and A. R. Newton, "A Multiprocessor Implementation of Relaxation-Based Electrical C;rcuit Simulation," Proc. of 21st DAC, Albuquerque, N.M., June, 1984, pp. 350-357.
[27]
P. K. U. Wang, "Approaches to Hardware Acceleration of Circuit Simulation," Proc. of ILEE ICCD, Port Chester, N.Y., October, 1985, pp. 724-727.
[28]
T. Cheung and J. E. Smith, "An Analysis of the Cray X-MP Memory System," Proc. of ICPP, Bellaire, Mich., August, 1984, pp. 499-505.
[29]
G. F. Pfister, W. C. 8rantley, D. A. George, S. L. Harvey, W. J. Kleinfelder, K. P. McAuliffe, E. A. Melton, V. A. Norton, and J. Weiss, "The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 764-771.
[30]
R. Maenner, "Hardware Task/Processor Scheduling in a Polyprocessor Environment," IEEE Tran. on Computers, vol. C-33, July, 1984.
[31]
A. Norton and G. F. Pfister, "A Methodology for Predicting Multiprocessor Performance," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 772-781.
[32]
S. P. Levitan, "Evaluation Criteria for Communication Structures in Parallel Architectures," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 147-154.
[33]
A. K. Ezzat and R. Agrawal, "Making Oneself Known in a Distributed World," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 139-142.
[34]
C. A. R. Hoare, '~Communicating Sequential Processes," Comm. ACM, pp. 666-677, August, 1978.
[35]
P. B. Hansen, "The Programming Language Concurrent Pascal," IEEE Tran. on Software Engineering, vol. SE-1, pp. 199-207, June, 1975.
[36]
H. Dietz and D. Klappholz, "Refining a Conventional Language for Race-Free Specification of Parallel Algorithms," Proc. of ICPP, Bellaire, Mich., August, 1984, pp. 380-382.
[37]
H. Dietz and D. Klappholz, "Refined C: A Sequential Language for Parallel Programming," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 442-448.
[38]
E. Kronstadt and G. Pfister, "Software Support for the Yorktown Simulation Engine," Proc. of 19th DAC, Las Vegas, Nev., June, 1982, pp. 6g- 64.
[39]
M. A. Franklin, D. F. Wann, and K. F. Wong, "Parallel Machines and Alqorithms for Discrete-Event Simulation," Proc. of ICPP, Bellaire, Mich., August, 1984, pp. 449-458.
[40]
R. R. Rezac, and L. T. Smith, "Methodology for & Results from the use of a Hardware Logic Simulation Engine," Proc. of IEEE ICCD, Port Chester, N.Y., October, 1984, pp. 457-461.
[41]
V. Ashok, R. Costello, and P. Sadyappan, "Distributed Discrete Event Simulation using Dataflow," Proc. of ICPP, St. Charles, III., August,
[42]
M. Vecchi and S. Kirkpatrick, "Global Wiring by Simulated Annealing," IEEE Tran. on CAD, vol. CAD-2, pp. 215-222, October, 1983.
[43]
P. M. Spira and C. Hage, "Hardware Acceleration of Gate Array Layout," Proc. of 22nd DAC, Las Vegas, Nev., June, 1985, pp. 359-366.
[44]
S. Nahar, S. Sahni, and E. Shagowitz, "Experiments with Simulated Annealing," Proc. of 22nd DAC, Las Vegas, Nev., June, 1985, pp. 748-752.
[45]
E. Felten, S. Karlin, and S. W. Otto, "The Traveling Salesman Problem on a Hypercubic, MIMD Computer," Proc. of ICPP, St. Charles, Ill., August, 1985, pp. 6-10.
[46]
R. A. Rutenbar and S. A. Kravitz, "Multiprocessor Placement by Simulated Annealing," Proc. of 23rd DAC, Las Vegas, Nev., June, 1986, These Proceedings.
[47]
P. B. Schneck, D. Austin, S. L. Squires, J. Lehmann, D Mizell, and K. Wallgren, "Parallel Processor Programs in the Federal Government," IEEE Computer, pp. 43-56, June, 1985.
[48]
D. D. Gajski and J-K. Peir, "Essential Issues in Multiprocessor Systems," IEEE Computer, pp. 9-27, June, 1985.
[49]
P. C. Patton, "Multiprocessors: Architecture and Applications," IEEE Computer, pp. 29-40, June, 1985.
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- Tutorial on parallel processing for design automation applications (tutorial session)
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Published: 02 July 1986
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