Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs
Abstract
3D-stacked wide I/O DRAM can significantly increase cell density and bandwidth while also lowering power consumption. However, 3D structures experience significant thermomechanical stress, which impacts circuit performance. This paper develops a procedure that performs a full performance analysis of 3D DRAMs, including latency, leakage power, refresh power, and area, while incorporating the effects of both layout-aware stress and layout-independent stress. The approach first proposes an analytic stress analysis method for the entire 3D DRAM structure, capturing the stress induced by TSVs, micro bumps, package bumps and warpage. Next, this stress is translated to variations in device mobility and threshold voltage, after which analytical models for latency, leakage power, and refresh power are derived. Finally, a complete analysis of performance variations is performed for various 3D DRAM layout configurations to assess the impact of layout-dependent stress.
References
[1]
U. Kang, et al., "8 Gb 3-D DDR3 DRAM using through-silicon-via technology," IEEE J Solid-St Circ, vol. 45, no. 1, pp. 111--119, 2010.
[2]
J.-S. Kim, et al., "A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4X 128 I/Os using TSV based stacking," IEEE J Solid-St Circ, vol. 47, no. 1, pp. 107--116, 2012.
[3]
D. U. Lee, et al., "A 1.2 V 8 Gb 8-channel 128 GB/s high-bandwidth memory (HBM) stacked DRAM with effective I/O test circuits," IEEE J Solid-St Circ, vol. 50, no. 1, pp. 191--203, 2015.
[4]
T. Zhang, et al., "3D-SWIFT: A high-performance 3D-stacked wide IO DRAM," in Proc. GLSVLSI, pp. 51--56, 2014.
[5]
S. J. Koester, 3D integration for VLSI systems. Pan Stanford, Singapore, 2011.
[6]
P. Garrou, et al., Handbook of 3D integration. Wiley, Weinheim, Germany, 2011.
[7]
Q. Zou, et al., "Thermomechanical stress-aware management for 3D IC designs," in Proc. DATE, pp. 1255--1258, 2013.
[8]
S. K. Marella and S. S. Sapatnekar, "A holistic analysis of circuit performance variations in 3D-ICs with thermal and TSV-induced stress considerations," IEEE T VLSI Syst, vol. 23, no. 7, pp. 1308--1321, 2015.
[9]
M. Jung, et al., "Chip/package mechanical stress impact on 3-D IC reliability and mobility variations," IEEE T Comput Aid D, vol. 32, no. 11, pp. 1694--1707, 2013.
[10]
Y. Sun, et al., "Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors," J Appl Phys, vol. 101, no. 10, 2007.
[11]
R. C. Jaeger, et al., "CMOS stress sensors on {100} silicon," IEEE J Solid St Circ, vol. 35, no. 1, pp. 85--95, 2000.
[12]
W. Zhang and J. G. Fossum, "On the threshold voltage of strained-Si-Si1-xGex MOSFETs," IEEE T Electron Dev, vol. 52, no. 2, pp. 263--268, 2005.
[13]
K. Chen, et al., "CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory," in Proc. DATE, pp. 33--38, 2012.
[14]
"CACTI tools." http://www.hpl.hp.com/research/cacti/.
[15]
S. Thoziyoor, et al., "CACTI 5.1," HPL-2008-20, HP Labs, Palo Alto, CA, 2008.
[16]
C. Herring and E. Vogt, "Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering," Phys Rev, vol. 101, no. 3, p. 944, 1956.
- Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs
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- CEDA: Council on Electronic Design Automation
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE-CAS: Circuits & Systems
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- IEEE-EDS: Electronic Devices Society
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Published: 13 November 2017
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ICCAD '17
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- SIGDA
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ICCAD '17: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN
November 13 - 16, 2017
California, Irvine
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