research-article

Standard cell library design and optimization methodology for ASAP7 PDK

Authors:

Greg YericAuthors Info & Claims

ICCAD '17: Proceedings of the 36th International Conference on Computer-Aided Design

Pages 999 - 1004

Published: 13 November 2017 Publication History

Abstract

Standard cell libraries are the foundation for the entire back-end design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and beyond, standard cell library design and optimization is becoming increasingly difficult due to extremely complex design constraints, as described in the ASAP7 process design kit (PDK). Notable complexities include discrete transistor sizing due to FinFETs, complicated design rules from lithography and restrictive layout space from modern standard cell architectures. The design methodology presented in this paper enables efficient and high-quality standard cell library design and optimization with the ASAP7 PDK. The key techniques include exhaustive transistor sizing for cell timing optimization, transistor placement with generalized Euler paths and back-end design prototyping for library-level explorations.

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Cited By

Hsu CGuo SLin YXu XLi MWang RHuang RPan DShin Y(2018)Layout-dependent aging mitigation for critical path timingProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201640(153-158)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201640
Li HChow WChen GYoung EYu B(2018)Routability-driven and fence-aware legalization for mixed-cell-height circuitsProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196107(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196107
Vashishtha VVangala MClark LParameswaran S(2017)ASAP7 predictive design kit development and cell design technology co-optimizationProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199837(992-998)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199837

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Published In

cover image ACM Conferences

ICCAD '17: Proceedings of the 36th International Conference on Computer-Aided Design

November 2017

1077 pages

Conference Chair:
Sri Parameswaran
GENERAL CHAIR

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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IEEE-EDS: Electronic Devices Society

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IEEE Press

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Published: 13 November 2017

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ICCAD '17

Sponsor:

CEDA
SIGDA
IEEE-CAS

ICCAD '17: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN

November 13 - 16, 2017

California, Irvine

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Hsu CGuo SLin YXu XLi MWang RHuang RPan DShin Y(2018)Layout-dependent aging mitigation for critical path timingProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201640(153-158)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201640
Li HChow WChen GYoung EYu B(2018)Routability-driven and fence-aware legalization for mixed-cell-height circuitsProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196107(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196107
Vashishtha VVangala MClark LParameswaran S(2017)ASAP7 predictive design kit development and cell design technology co-optimizationProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199837(992-998)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199837

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