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Selective cache ways: on-demand cache resource allocation

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David H. AlbonesiAuthors Info & Claims

MICRO 32: Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture

Pages 248 - 259

Published: 16 November 1999 Publication History

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Abstract

Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application requirements. Selective cache ways provides the ability to disable a subset of the ways in a set associative cache during periods of modest cache activity, while the full cache may remain operational for more cache-intensive periods. Because this approach leverages the subarray partitioning that is already present for performance reasons, only minor changes to a conventional cache are required, and therefore, full-speed cache operation can be maintained. Furthermore, the tradeoff between performance and energy is flexible, and can be dynamically tailored to meet changing application and machine environmental conditions. We show that trading off a small performance degradation for energy savings can produce a significant reduction in cache energy dissipation using this approach.

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Cited By

Huang ZJoao JRico AHilton ALee B(2019)DynaSprintProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358301(426-439)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358301
Egawa RSaito RSato MKobayashi H(2019)A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass MechanismProceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies10.1145/3337801.3337820(1-6)Online publication date: 6-Jun-2019
https://dl.acm.org/doi/10.1145/3337801.3337820
Park JLee MKim SJu MHong J(2019)MH CacheACM Transactions on Architecture and Code Optimization10.1145/332852016:3(1-26)Online publication date: 18-Jul-2019
https://dl.acm.org/doi/10.1145/3328520
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Index Terms

Selective cache ways: on-demand cache resource allocation
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM Conferences

MICRO 32: Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture

November 1999

299 pages

ISBN:076950437X

Chairmen:
Ronny Ronen
Intel Israel
,
Matthew Farrens
Univ. of California, Davis
,
Ilan Spillinger
Intel Israel

Copyright © Copyright (c) 1998 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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IEEE TC - MICRO: IEEE TC - MICRO
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

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IEEE Computer Society

United States

Publication History

Published: 16 November 1999

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MICRO99

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IEEE TC - MICRO
SIGMICRO

MICRO99: 32nd Annual ACM/IEEE International Symposium on Microarchitecture

November 16 - 18, 1999

Haifa, Israel

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MICRO 32 Paper Acceptance Rate 27 of 131 submissions, 21%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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November 2 - 6, 2024

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Cited By

Huang ZJoao JRico AHilton ALee B(2019)DynaSprintProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358301(426-439)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358301
Egawa RSaito RSato MKobayashi H(2019)A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass MechanismProceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies10.1145/3337801.3337820(1-6)Online publication date: 6-Jun-2019
https://dl.acm.org/doi/10.1145/3337801.3337820
Park JLee MKim SJu MHong J(2019)MH CacheACM Transactions on Architecture and Code Optimization10.1145/332852016:3(1-26)Online publication date: 18-Jul-2019
https://dl.acm.org/doi/10.1145/3328520
Thomas SMcGuinness RVoelker GPorter GBenson TZilberman N(2018)Dark packets and the end of network scalingProceedings of the 2018 Symposium on Architectures for Networking and Communications Systems10.1145/3230718.3230727(1-14)Online publication date: 23-Jul-2018
https://dl.acm.org/doi/10.1145/3230718.3230727
Young VChou CJaleel AQureshi M(2018)ACCORDProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00036(328-339)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00036
Patsilaras GTuck J(2017)ReDirectACM Transactions on Architecture and Code Optimization10.1145/316201514:4(1-23)Online publication date: 20-Dec-2017
https://dl.acm.org/doi/10.1145/3162015
Tsai PBeckmann NSanchez D(2017)JengaACM SIGARCH Computer Architecture News10.1145/3140659.308021445:2(652-665)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080214
Tsai PBeckmann NSanchez D(2017)JengaProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080214(652-665)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3079856.3080214
Choi IYeung D(2017)Multi-cache resizing via greedy coordinate descentThe Journal of Supercomputing10.1007/s11227-016-1927-073:6(2402-2429)Online publication date: 1-Jun-2017
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Laurenzano MZhang YChen JTang LMars J(2016)PowerChopACM SIGARCH Computer Architecture News10.1145/3007787.300115244:3(140-152)Online publication date: 18-Jun-2016
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