Flip-chip routing with IO planning considering practical pad assignment constraints
Pages 521 - 526
Abstract
In order to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs, the flip chip package is used and provides the highest chip density compared to other packaging technologies. In this paper, we propose the first work of free-assignment flip-chip routing considering practical bump/IO pad constraints and flexibilities. Unlike previous studies regarding all nets as the same, we differentiate signal and power/ground nets and set different bump pad assignment constraints for substrate layout optimization. In our flow, a global routing-based IO-bump assignment algorithm is proposed with a multi-commodity flow network model. After that, a detailed routing algorithm minimizing total wirelength is presented, which determines optimal relay points with a linear programming (LP) formulation. Finally, a dynamic programming (DP)-based IO pad planning technique is applied to further reduce the number of wire bends. Experimental results based on modified industrial cases show that our algorithm flow not only achieves 100% routability of all testcases but also minimizes total wirelength and bump utilization.
References
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- SIGDA: ACM Special Interest Group on Design Automation
- IEEE Council on Electronic Design Automation (CEDA)
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Published: 22 January 2018
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ASPDAC '18: 23rd Asia and South Pacific Design Automation Conference
January 22 - 25, 2018
Jeju, Republic of Korea
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