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Comparing frequency scaling efficacy on different memory technologies

Published: 29 April 2019 Publication History

Abstract

Dual inline memory modules (DIMMs) built with double data rate of the 4th generation (DDR4) synchronous dynamic random access memory (SDRAM) are widely used in current memory components in the high performance computing (HPC) systems. Since modern parallel applications are becoming more data intensive, improvements in memory technology are crucial for sustained high performance. DDR4 provides higher reliability, availability, and serviceability than other DDR memories do so. DDR4 essentially operates at a higher frequency and lower voltage compared with its previous generations. Therefore, for a given application, the memory intensities (measured as a number of memory accesses per micro-operation retired) of DDR3 and DDR4 may differ significantly. In this paper, the difference in memory intensity between DDR3 and DDR4 is explored along with the relative difference in the off-chip time each platform provides to facilitate frequency scaling.

References

[1]
Bhati, I., M. Chang, Z. Chishti, S. Lu, and B. Jacob. 2016, Jan. "DRAM Refresh Mechanisms, Penalties, and Trade-Offs". IEEE Transactions on Computers vol. 65 (1), pp. 108--121.
[2]
Choi, K., R. Soma, and M. Pedram. 2005. "Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times". Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on vol. 24 (1), pp. 18 -- 28.
[3]
M. David January 2019. "Putting Your Data and Code in Order". https://software.intel.com/en-us/articles/putting-your-data-and-code-in-order-optimization-and-memory-part-1. {Online; accessed 1-January-2019}.
[4]
Freeh, V., and D. Lowenthal. 2005. "Using multiple energy gears in MPI programs on a power-scalable cluster". In Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, pp. 164--173.
[5]
Ge, R., X. Feng, W. Feng, and K. Cameron. 2007, Sep. "CPU MISER: A Performance-Directed, Run-Time System for Power-Aware Clusters". In Parallel Processing, 2007. ICPP 2007. International Conference on, pp. 18.
[6]
Ge, R., X. Feng, S. Song, H. Chang, D. Li, and K. Cameron. 2010. "PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications". Parallel and Distributed Systems, IEEE Transactions on vol. 21, pp. 658--671.
[7]
Hsu, C., and W. Feng. 2005, Nov. "A Power-Aware Run-Time System for High-Performance Computing". In Supercomputing, 2005. Proceedings of the ACM/IEEE SC 2005 Conference, pp. 1.
[8]
Huang, S., and W. Feng. 2009, May. "Energy-Efficient Cluster Computing via Accurate Workload Characterization". In Cluster Computing and the Grid, 2009. CCGRID'09. 9th IEEE/ACM International Symposium on, pp. 68--75.
[9]
Jacob, B., S. Ng, and D. Wang. 2007. Memory Systems: Cache, DRAM, Disk. San Francisco, CA, USA, Morgan Kaufmann Publishers Inc.
[10]
JEDEC January 2019a. "DDR3 Standard, JESD79-3F". https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf. {Online; accessed 3-January-2019}.
[11]
JEDEC January 2019b. "DDR4 Standard, JESD79-4". https://www.jedec.org/sites/default/files/docs/JESD79-4.pdf. {Online; accessed 3-January-2019}.
[12]
Kim, G., J. Feng, M. Mokhtaari, J. Adhyaru, R. Shaikh, B. Natarajan, and D. Oh. 2016, Fourth. "Analysis and comparison of DDR3/DDR4 clock duty-cycle-distortion (DCD) for UDIMM and discrete SDRAM component configurations". IEEE Electromagnetic Compatibility Magazine vol. 5 (4), pp. 133--139.
[13]
Lim, M., V. Freeh, and D. Lowenthal. 2006. "Adaptive, transparent frequency and voltage scaling of communication phases in MPI programs". In Proceedings of the 2006 ACM/IEEE conference on Supercomputing.
[14]
McVoy, L., and C. Staelin. 1996. "Lmbench: Portable Tools for Performance Analysis". In Proceedings of the 1996 Annual Conference on USENIX Annual Technical Conference, ATEC '96, pp. 23--23. Berkeley, CA, USA, USENIX Association.
[15]
Ian Poole December 2018. "DDR4 Memory". https://www.radio-electronics.com/info/data/semicond/memory/sdram-ddr4-memory.php. {Online; accessed 20-December-2018}.
[16]
R.M. Olson, M. S., M. Gordon, and A. Rendell. 2003, Nov. "Enabling the Efficient Use of SMP Clusters: The GAMESS/DDI Model". In Supercomputing, 2003 ACM/IEEE Conference, pp. 41.
[17]
Schmidt, M. W., K. Baldridge, J. Boatz, S. Elbert, M. Gordon, J. Jensen, S. Koseki, N. Matsunaga, K. Nguyen, S. Su, T. Windus, M. Dupuis, and J. J. Montgomery. 1993, Nov. "General atomic and molecular electronic structure system". J. Comput. Chem. vol. 14, pp. 1347--1363.
[18]
Sundriyal, V., and M. Sosonkina. 2016. "Joint Frequency Scaling of Processor and DRAM". The Journal of Supercomputing vol. 72 (4), pp. 1549--1569.
[19]
Sundriyal, V., M. Sosonkina, F. Liu, and M. Schmidt. 2011. "Dynamic Frequency Scaling and Energy Saving in Quantum Chemistry Applications". In Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum, IPDPSW '11, pp. 837--845. Washington, DC, USA, IEEE Computer Society.
[20]
V. Vishwanathan July 2017. "Intel Memory Latency Checker". https://software.intel.com/en-us/articles/intelr-memory-latency-checker. {Online; accessed 27-November-2017}.
[21]
Wulf, W., and S. A. McKee. 1994. "Hitting the Memory Wall: Implications of the Obvious". Technical report, Charlottesville, VA, USA.
[22]
Zhang, C., and X. Guo. 2017, July. "Enabling efficient fine-grained DRAM activations with interleaved I/O". In 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1--6.
[23]
Zhang, Z., and J. M. Chang. 2014, May. "A Cool Scheduler for Multi-Core Systems Exploiting Program Phases". IEEE Transactions on Computers vol. 63 (5), pp. 1061--1073.

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cover image Guide Proceedings
HPC '19: Proceedings of the High Performance Computing Symposium
April 2019
173 pages

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Society for Computer Simulation International

San Diego, CA, United States

Publication History

Published: 29 April 2019

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