research-article

Prospector: synthesizing efficient accelerators via statistical learning

Authors:

Atefeh Mehrabi,

Aninda Manocha,

Benjamin C. Lee,

Daniel J. SorinAuthors Info & Claims

DATE '20: Proceedings of the 23rd Conference on Design, Automation and Test in Europe

Pages 151 - 156

Published: 26 June 2020 Publication History

Abstract

Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. High-level synthesis automatically generates hardware from code. Reconfigurable fabrics instantiate accelerators while avoiding fabrication costs for custom circuits. We further reduce design effort with statistical learning. We build an automated framework, called Prospector, that uses Bayesian techniques to optimize synthesis directives, reducing execution latency and resource usage in field-programmable gate arrays. We show in a certain amount of time designs discovered by Prospector are closer to Pareto-efficient designs compared to prior approaches.

References

[1]

Spearmint: https://github.com/HIPS/Spearmint/tree/PESM.

[2]

G. Ascia, V. Catania, and M. Palesi, "A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 635--645, 2005.

Digital Library

[3]

J. Bergstra and Y. Bengio, "Random search for hyper-parameter optimization," Journal of Machine Learning Research, 2012.

[4]

P. Bosman and D. Thierens, "The balance between proximity and diversity in multiobjective evolutionary algorithms," IEEE Transactions on Evolutionary Computation, 2003.

Digital Library

[5]

K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: Nsga-ii," IEEE Transactions on Evolutionary Computation, 2002.

Digital Library

[6]

D. Hernández-Lobato, J. Hernandez-Lobato, A. Shah, and R. Adams, "Predictive entropy search for multi-objective bayesian optimization," in Proc. International Conference on Machine Learning, 2016.

[7]

D. Koeplinger, R. Prabhakar, Y. Zhang, C. Delimitrou, C. Kozyrakis, and K. Olukotun, "Automatic generation of efficient accelerators for re-configurable hardware," in Proc. International Symposium on Computer Architecture (ISCA), 2016.

Digital Library

[8]

B. Lee and D. Brooks, "Illustrative design space studies with microarchitectural regression models," in Proc. International Symposium on High-Performance Computer Architecture (HPCA), 2007.

[9]

H. Liu and L. Carloni, "On learning-based methods for design-space exploration with high-level synthesis," in Proc. Design Automation Conference (DAC), 2013.

Digital Library

[10]

C. Lo and P. Chow, "Model-based optimization of high level synthesis directives," in Proc. International Conference on Field Programmable Logic and Applications (FPL), 2016.

[11]

M. Palesi and T. Givargis, "Multi-objective design space exploration using genetic algorithms," in Proceedings of the tenth international symposium on Hardware/software codesign. ACM, 2002, pp. 67--72.

[12]

L. Pouchet, "Polybench: The polyhedral benchmark suite," PolyBench: http://www.cs.ucla.edu/pouchet/software/polybench, 2012.

[13]

B. Reagen, R. Adolf, Y. Shao, G. Wei, and D. Brooks, "Machsuite: Benchmarks for accelerator design and customized architectures," in Proc. International Symposium on Workload Characterization, 2014.

[14]

B. Reagen, J. Hernández-Lobato, R. Adolf, M. Gelbart, P. Whatmough, G. Wei, and D. Brooks, "A case for efficient accelerator design space exploration via bayesian optimization," in Proc. International Symposium on Low Power Electronics and Design (ISLPED), 2017.

[15]

B. Reagen, Y. Shao, G. Wei, and D. Brooks, "Quantifying acceleration: Power/performance trade-offs of application kernels in hardware," in Proc. International Symposium on Low Power Electronics and Design (ISLPED), 2013.

[16]

B. Schafer, T. Takenaka, and K. Wakabayashi, "Adaptive simulated annealer for high level synthesis design space exploration," in Proc. International Symposium on VLSI Design, Automation and Test, 2009.

[17]

B. Schafer and K. Wakabayashi, "Machine learning predictive modelling high-level synthesis design space exploration," IET Computers & Digital Techniques, 2012.

[18]

B. Shahriari, K. Swersky, Z. Wang, R. Adams, and N. D. Freitas, "Taking the human out of the loop: A review of bayesian optimization," Proceedings of the IEEE, 2016.

[19]

Y. Shao, B. Reagen, G. Wei, and D. Brooks, "Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures," in Proc. International Symposium on Computer Architecture (ISCA), 2014.

Digital Library

[20]

F. Winterstein, S. Bayliss, and G. Constantinides, "High-level synthesis of dynamic data structures: A case study using vivado hls," in Proc. International Conference on Field-Programmable Technology, 2013.

[21]

J. Zhao, L. Feng, S. Sinha, W. Zhang, Y. Liang, and B. He, "Comba: A comprehensive model-based analysis framework for high level synthesis of real applications," in Proceedings of the 36th International Conference on Computer-Aided Design, 2017.

[22]

G. Zhong, A. Prakash, Y. Liang, T. Mitra, and S. Niar, "Lin-analyzer: a high-level performance analysis tool for fpga-based accelerators," in Proceedings of the 53rd Annual Design Automation Conference. ACM, 2016, p. 136.

Cited By

Wu NXie Y(2022)A Survey of Machine Learning for Computer Architecture and SystemsACM Computing Surveys10.1145/349452355:3(1-39)Online publication date: 3-Feb-2022
https://dl.acm.org/doi/10.1145/3494523
Lai YUstun EXiang SFang ZRong HZhang Z(2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
https://dl.acm.org/doi/10.1145/3469660

Index Terms

Prospector: synthesizing efficient accelerators via statistical learning
1. Hardware
  1. Electronic design automation

Index terms have been assigned to the content through auto-classification.

Recommendations

From software to accelerators with LegUp high-level synthesis
CASES '13: Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level ...
A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom ...
Bayesian Optimization for Efficient Accelerator Synthesis

Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. High-level synthesis automatically generates hardware from code. Reconfigurable ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '20: Proceedings of the 23rd Conference on Design, Automation and Test in Europe

March 2020

1788 pages

ISBN:9783981926347

General Chairs:
Giorgio Di Natale
CNRS/TIMA, FR
,
Franco Fummi
University of Verona, IT

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

EDAA: European Design Automation Association
EDAC: Electronic Design Automation Consortium
IEEE CEDA
The Russian Academy of Sciences: The Russian Academy of Sciences
ECSI: European Electronic Chips & Systems design Initiative

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 26 June 2020

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DATE '20

Sponsor:

SIGDA

DATE '20: Design, Automation and Test in Europe

March 9 - 13, 2020

Grenoble, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
29
Total Downloads

Downloads (Last 12 months)6
Downloads (Last 6 weeks)0

Reflects downloads up to 30 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Wu NXie Y(2022)A Survey of Machine Learning for Computer Architecture and SystemsACM Computing Surveys10.1145/349452355:3(1-39)Online publication date: 3-Feb-2022
https://dl.acm.org/doi/10.1145/3494523
Lai YUstun EXiang SFang ZRong HZhang Z(2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
https://dl.acm.org/doi/10.1145/3469660

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents