research-article

Co-exploration of neural architectures and heterogeneous ASIC accelerator designs targeting multiple tasks

Authors:

Tushar Krishna,

Vikas ChandraAuthors Info & Claims

DAC '20: Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference

Article No.: 163, Pages 1 - 6

Published: 18 November 2020 Publication History

Abstract

Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs). However, it remains an open problem how to integrate NAS with Application-Specific Integrated Circuits (ASICs), despite them being the most powerful AI accelerating platforms. The major bottleneck comes from the large design freedom associated with ASIC designs. Moreover, with the consideration that multiple DNNs will run in parallel for different workloads with diverse layer operations and sizes, integrating heterogeneous ASIC sub-accelerators for distinct DNNs in one design can significantly boost performance, and at the same time further complicate the design space. To address these challenges, in this paper we build ASIC template set based on existing successful designs, described by their unique dataflows, so that the design space is significantly reduced. Based on the templates, we further propose a framework, namely ASICNAS, which can simultaneously identify multiple DNN architectures and the associated heterogeneous ASIC accelerator design, such that the design specifications (specs) can be satisfied, while the accuracy can be maximized. Experimental results show that compared with successive NAS and ASIC design optimizations which lead to design spec violations, ASICNAS can guarantee the results to meet the design specs with 17.77%, 2.49×, and 2.32× reductions on latency, energy, and area and less than 1.6% accuracy loss. To the best of the authors' knowledge, this is the first work on neural architecture and ASIC accelerator design co-exploration.

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Cited By

Venieris SFernandez-Marques JLane N(2023)Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights GenerationACM Transactions on Design Automation of Electronic Systems10.1145/361167328:6(1-31)Online publication date: 16-Oct-2023
https://dl.acm.org/doi/10.1145/3611673
Bhattacharjee AMoitra APanda P(2023) XploreNAS: Explore Adversarially Robust and Hardware-efficient Neural Architectures for Non-ideal XbarsACM Transactions on Embedded Computing Systems10.1145/359304522:4(1-17)Online publication date: 24-Jul-2023
https://dl.acm.org/doi/10.1145/3593045
Chen WWang YXu YGao CLiu CZhang L(2022)A Framework for Neural Network Architecture and Compile Co-optimizationACM Transactions on Embedded Computing Systems10.1145/353325122:1(1-24)Online publication date: 29-Oct-2022
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Published In

cover image ACM Conferences

DAC '20: Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference

July 2020

1545 pages

ISBN:9781450367257

General Chair:
Zhuo Li
Cadence Design Systems, Inc., Austin, TX

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IEEE-CEDA

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IEEE Press

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Published: 18 November 2020

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DAC '20

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DAC '20: The 57th Annual Design Automation Conference 2020

July 20 - 24, 2020

Virtual Event, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Venieris SFernandez-Marques JLane N(2023)Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights GenerationACM Transactions on Design Automation of Electronic Systems10.1145/361167328:6(1-31)Online publication date: 16-Oct-2023
https://dl.acm.org/doi/10.1145/3611673
Bhattacharjee AMoitra APanda P(2023) XploreNAS: Explore Adversarially Robust and Hardware-efficient Neural Architectures for Non-ideal XbarsACM Transactions on Embedded Computing Systems10.1145/359304522:4(1-17)Online publication date: 24-Jul-2023
https://dl.acm.org/doi/10.1145/3593045
Chen WWang YXu YGao CLiu CZhang L(2022)A Framework for Neural Network Architecture and Compile Co-optimizationACM Transactions on Embedded Computing Systems10.1145/353325122:1(1-24)Online publication date: 29-Oct-2022
https://dl.acm.org/doi/10.1145/3533251
Chitty-Venkata KSomani A(2022)Neural Architecture Search Survey: A Hardware PerspectiveACM Computing Surveys10.1145/352450055:4(1-36)Online publication date: 21-Nov-2022
https://dl.acm.org/doi/10.1145/3524500
Zhang DHuda SSonghori EPrabhu KLe QGoldie AMirhoseini AFalsafi BFerdman MLu SWenisch T(2022)A full-stack search technique for domain optimized deep learning acceleratorsProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507767(27-42)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507767
Bringmann OEcker WFeldner IFrischknecht AGerum CHämäläinen THanif MKlaiber MMueller-Gritschneder DBernardo PPrebeck SShafique MXue JYang C(2021)Automated HW/SW co-design for edge AIProceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis10.1145/3478684.3479261(11-20)Online publication date: 30-Sep-2021
https://dl.acm.org/doi/10.1145/3478684.3479261
Mendis HKang CHsiu P(2021)Intermittent-Aware Neural Architecture SearchACM Transactions on Embedded Computing Systems10.1145/347699520:5s(1-27)Online publication date: 17-Sep-2021
https://dl.acm.org/doi/10.1145/3476995
Tu CSun QChang H(2021)RAP: A Software Framework of Developing Convolutional Neural Networks for Resource-constrained Devices Using Environmental Monitoring as a Case StudyACM Transactions on Cyber-Physical Systems10.1145/34726125:4(1-28)Online publication date: 22-Sep-2021
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Zhang YFu YJiang WLi CYou HLi MChandra VLin Y(2021)DIANProceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design10.1109/ISLPED52811.2021.9502478(1-6)Online publication date: 26-Jul-2021
https://dl.acm.org/doi/10.1109/ISLPED52811.2021.9502478

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