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Building an on-chip deep learning memory hierarchy brick by brick: late breaking results

Published: 18 November 2020 Publication History

Abstract

Data accesses between on- and off-chip memories account for a large fraction of overall energy consumption during inference with deep learning networks. We present Boveda, a lossless on-chip memory compression technique for neural networks operating on fixed-point values. Boveda reduces the datawidth used per block of values to be only as long as necessary: since most values are of small magnitude Boveda drastically reduces their footprint. Boveda can be used to increase the effective on-chip capacity, to reduce off-chip traffic, or to reduce the on-chip memory capacity needed to achieve a performance/energy target. Boveda reduces total model footprint to 53%.

References

[1]
A. R. Alameldeen and D. A. Wood, "Frequent pattern compression: A significance-based compression scheme for l2 caches," 2004.
[2]
G. Pekhimenko and et al., "Base-delta-immediate compression: Practical data compression for on-chip caches," in Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, ser. PACT '12. New York, NY, USA: ACM, 2012, pp. 377--388.

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cover image ACM Conferences
DAC '20: Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference
July 2020
1545 pages
ISBN:9781450367257
  • General Chair:
  • Zhuo Li

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  • IEEE-CEDA

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IEEE Press

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Published: 18 November 2020

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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