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View all- Keitel-Schulz DWehn N(1998)Issues in embedded DRAM development and applicationsProceedings of the 11th international symposium on System synthesis10.5555/293016.293021(23-31)Online publication date: 2-Dec-1998
Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions
Author: 
F. CatthoorAuthors Info & Claims
F. CatthoorAuthors Info & ClaimsAbstract
Both in custom and programmable instruction-set processors for data-dominated multi-media applications, many of the architecture components are intended to solve the data transfer and storage issues. Recent experiments at several locations have clearly demonstrated that due to this fact, the main power (and largely also area) cost is situated in the memory units and the communication hardware. In this paper, the main reasons for this problem will be reviewed and a perspective will be provided on the expected near-future evolution. It will be shown that the circuit and process technology advances have been very significant in the past decade. Still, these are not sufficient to fully solve this power and area bottle-neck which has been created in the same period. Therefore, also several possible design methodology remedies will be proposed for this critical design issue, with emphasis on effective system-level memory management methodologies. These promise very large savings on energy-delay also on area for multi-media applications, while still meeting the real-time constraints.
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Index Terms
- Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions
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Published: 23 February 1998
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View all- Keitel-Schulz DWehn N(1998)Issues in embedded DRAM development and applicationsProceedings of the 11th international symposium on System synthesis10.5555/293016.293021(23-31)Online publication date: 2-Dec-1998
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