Specification and verification of asynchronous circuits using marked graphs

Specification and Description Language (SDL) is a standardised formal description technique for telecommunications software. ObjectGEODE is a commercial toolset which supports software design using SDL. This article presents a way of using SDL and ...

This paper presents a method of formally specifying, refining and verifying concurrent systems which uses the object-oriented state-based specification language Object-Z together with the process algebra CSP. Object-Z provides a convenient way of ...

Although the formal method VDM has been in existence since the 1970s, there are still no satisfactory tools to support verification in VDM. The paper deals with one possible means of approaching this problem by using the PVS theorem-prover. It describes ...