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Logic BIST for Large Industrial Designs: Real Issues and Case Studies

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Janusz RajskiAuthors Info & Claims

ITC '99: Proceedings of the 1999 IEEE International Test Conference

Page 358

Published: 28 September 1999 Publication History

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Abstract

This paper discusses practical issues involved in applyinglogic built-in self-test (BIST) to four large industrialdesigns. These multi-clock designs, ranging in size from200K to 800K gates, pose significant challenges to logicBIST methodology, flow, and tools. The paper presents theprocess of generating a BIST-compliant core along with thelogic BIST controller for at-speed testing. Comparativedata on fault grades and area overhead between automatictest pattern generation (ATPG) and logic BIST arereported. The experimental results demonstrate that withautomation of the proposed solutions, logic BIST canachieve test quality approaching that of ATPG with minimalarea overhead and few changes to the design flow.

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Ozer EVenu BIturbe XDas SLyberis SBiggs JHarrod PPenton JOskin MInoue K(2018)Error correlation prediction in lockstep processors for safety-critical systemsProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00065(737-748)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00065
Omana MRossi DFuzzi FMetra CTirumurti CGalivanche R(2017)Scalable Approach for Power Droop Reduction During Scan-Based Logic BISTIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.257260625:1(238-246)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2572606
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
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Logic BIST for Large Industrial Designs: Real Issues and Case Studies
1. Hardware

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ITC '99: Proceedings of the 1999 IEEE International Test Conference

September 1999

ISBN:0780357531

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IEEE Computer Society

United States

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Published: 28 September 1999

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Ozer EVenu BIturbe XDas SLyberis SBiggs JHarrod PPenton JOskin MInoue K(2018)Error correlation prediction in lockstep processors for safety-critical systemsProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00065(737-748)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00065
Omana MRossi DFuzzi FMetra CTirumurti CGalivanche R(2017)Scalable Approach for Power Droop Reduction During Scan-Based Logic BISTIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.257260625:1(238-246)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2572606
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
Cui ALuo YLi HQu G(2017)Why current secure scan designs fail and how to fix them?Integration, the VLSI Journal10.1016/j.vlsi.2016.10.01156:C(105-114)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.10.011
Çakir BMalik SNebel WAtienza D(2015)Hardware trojan detection for gate-level ICs using signal correlation based clusteringProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755860(471-476)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755860
Gorev MUbar REllervee PDevadze SRaik JMin M(2015)Functional self-test of high-performance pipe-lined signal processing architecturesMicroprocessors & Microsystems10.1016/j.micpro.2014.11.00239:8(909-918)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1016/j.micpro.2014.11.002
Wu SWang LWen XJone WHsiao MLi FLi JHuang J(2012)Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock DomainsACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885217:4(1-16)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2348839.2348852
Alves DBarros ESaraiva IRibas RPlett C(2009)A logic built-in self-test architecture that reuses manufacturing compressed scan test patternsProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601923(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601923
Banga MChandrasekar MFang LHsiao MNarayanan VYan ZMacii EBhanja S(2008)Guided test generation for isolation and detection of embedded trojans in icsProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366196(363-366)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366196
Imhof MZoellin CWunderlich HMaeding NLeenstra JLevitan S(2007)Scan test planning for power reductionProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278614(521-526)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278614
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