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Almatrood A and Singh H (2018). Design of Generalized Pipeline Cellular Array in Quantum-Dot Cellular Automata, IEEE Computer Architecture Letters, 17:1, (29-32), Online publication date: 1-Jan-2018.

Vassalos E and Bakalis D On the design of modulo 2n-1 cubing units Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, (251-256)

Vassalos E and Bakalis D (2012). CSD-RNS-based Single Constant Multipliers, Journal of Signal Processing Systems, 67:3, (255-268), Online publication date: 1-Jun-2012.

Patronik P, Berezowski K, Piestrak S, Biernat J and Shrivastava A Fast and energy-efficient constant-coefficient FIR filters using residue number system Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design, (385-390)

Singh M, Tierno J, Rylyakov A, Rylov S and Nowick S (2018). An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18:7, (1043-1056), Online publication date: 1-Jul-2010.

Wu C Fast Parallel Montgomery Binary Exponentiation Algorithm Using Canonical- Signed-Digit Recoding Technique Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing, (428-438)

Angotzi G, Barbaro M and Jespers P Comparison of redundant architectures for two-step ADCs Proceedings of the 18th ACM Great Lakes symposium on VLSI, (445-450)

Lai C, Huang C and Khoo K Improving constant-coefficient multiplier verification by partial product identification Proceedings of the conference on Design, automation and test in Europe, (813-818)

Hauck S and DeHon A (2007). Reconfigurable Computing, 10.5555/1564780, Online publication date: 2-Nov-2007.

Carneiro D, Pinheiro P, Prudêncio P, Cavalcante D, Sousa D, Braquehais R, Marrocos T and Fernandez M IP-checksum incremental update method proposal for efficient use of energy in wireless environments Proceedings of the 2007 Euro American conference on Telematics and information systems, (1-7)

Wey C, Lin S and Shiue M A pipelined divider with a small lookup table Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems, (181-185)

Williams T, Ahmadi M and Miller W (2007). Design of 2D FIR and IIR Digital Filters with Canonical Signed Digit Coefficients Using Singular Value Decomposition and Genetic Algorithms, Circuits, Systems, and Signal Processing, 26:1, (69-89), Online publication date: 1-Feb-2007.

Kang J and Gaudiot J (2006). A Simple High-Speed Multiplier Design, IEEE Transactions on Computers, 55:10, (1253-1258), Online publication date: 1-Oct-2006.

Enomoto T and Kobayashi N A low dynamic power and low leakage power 90-nm CMOS square-root circuit Proceedings of the 2006 Asia and South Pacific Design Automation Conference, (90-91)

Khabbazian M, Gulliver T and Bhargava V (2005). A New Minimal Average Weight Representation for Left-to-Right Point Multiplication Methods, IEEE Transactions on Computers, 54:11, (1454-1459), Online publication date: 1-Nov-2005.

Manku G and Sawada J A loopless gray code for minimal signed-binary representations Proceedings of the 13th annual European conference on Algorithms, (438-447)

Kang J and Gaudiot J A logarithmic time method for two's complementation Proceedings of the 5th international conference on Computational Science - Volume Part I, (212-219)

Han W, Erdogan A, Arslan T and Hasan M The development of high performance FFT IP cores through hybrid low power algorithmic methodology Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (549-552)

Hosangadi A, Fallah F and Kastner R Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (523-528)

Ferrari A, Almeida R and Martins R Extensible multiplier-accumulator blocks for FPGAs Proceedings of the 4th international symposium on Information and communication technologies, (154-159)

Rosa V, Costa E, Monteiro J and Bampi S An improved synthesis method for low power hardwired FIR filters Proceedings of the 17th symposium on Integrated circuits and system design, (237-241)

Shin K and Kim T (2018). Tight integration of timing-driven synthesis and placement of parallel multiplier circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12:7, (766-775), Online publication date: 1-Jul-2004.

Phillips B and Burgess N (2004). Minimal Weight Digit Set Conversions, IEEE Transactions on Computers, 53:6, (666-677), Online publication date: 1-Jun-2004.

Nève A, Schettler H, Ludwig T and Flandre D (2018). Power-delay product minimization in high-performance 64-bit carry-select adders, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12:3, (235-244), Online publication date: 1-Mar-2004.

Porto R and Agostini L Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation Proceedings of the conference on Design, automation and test in Europe - Volume 3

Shin K and Kim T An integrated approach to timing-driven synthesis and placement of arithmetic circuits Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (155-158)

Aoki T, Homma N and Higuchi T (2019). Evolutionary Synthesis of Arithmetic Circuit Structures, Artificial Intelligence Review, 20:3-4, (199-232), Online publication date: 1-Dec-2003.

Hiasat A (2018). An arithmetic residue to binary conversion technique, Integration, the VLSI Journal, 36:1-2, (13-25), Online publication date: 1-Sep-2003.

Vergos H, Nikolos D, Bellos M and Efstathiou C (2003). Deterministic BIST for RNS Adders, IEEE Transactions on Computers, 52:7, (896-906), Online publication date: 1-Jul-2003.

Hiasat A and Sweidan A (2018). Residue number system to binary converter for the moduli set (2n-1, 2n - 1, 2n + 1), Journal of Systems Architecture: the EUROMICRO Journal, 49:1-2, (53-58), Online publication date: 1-Jul-2003.

Vergos H, Efstathiou C and Nikolos D (2002). Diminished-One Modulo 2^n +1 Adder Design, IEEE Transactions on Computers, 51:12, (1389-1399), Online publication date: 1-Dec-2002.

Um J and Kim T Layout-aware synthesis of arithmetic circuits Proceedings of the 39th annual Design Automation Conference, (207-212)

Azouaoui O and Chohra A (2019). Soft Computing Based Pattern Classifiers for the Obstacle Avoidance Behavior of Intelligent Autonomous Vehicles (IAV), Applied Intelligence, 16:3, (249-272), Online publication date: 27-Feb-2002.

Hiasat A (2002). High-Speed and Reduced-Area Modular Adder Structures for RNS, IEEE Transactions on Computers, 51:1, (84-89), Online publication date: 1-Jan-2002.

Bakalis D, Adaos K, Alexiou G, Nikolos D and Lymperopoulos D EUDOXUS Proceedings of the 12th International Workshop on Rapid System Prototyping

Park I and Kang H Digital filter synthesis based on minimal signed digit representation Proceedings of the 38th annual Design Automation Conference, (468-473)

Um J and Kim T (2001). An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits, IEEE Transactions on Computers, 50:3, (215-233), Online publication date: 1-Mar-2001.

Wang H Fixed-Width Multiplier for DSP Application Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Joye M and Yen S (2000). Optimal Left-to-Right Binary Signed-Digit Recoding, IEEE Transactions on Computers, 49:7, (740-748), Online publication date: 1-Jul-2000.

Yeh W and Jen C (2000). High-Speed Booth Encoded Parallel Multiplier Design, IEEE Transactions on Computers, 49:7, (692-701), Online publication date: 1-Jul-2000.

Kalampoukas L, Nikolos D, Efstathiou C, Vergos H and Kalamatianos J (2000). High-Speed Parallel-Prefix Modulo 2n - 1 Adders, IEEE Transactions on Computers, 49:7, (673-680), Online publication date: 1-Jul-2000.

Cheng F, Unger S and Theobald M (2000). Self-Timed Carry-Lookahead Adders, IEEE Transactions on Computers, 49:7, (659-672), Online publication date: 1-Jul-2000.

Cotofana S and Vassiliadis S (2000). Signed Digit Addition and Related Operations with Threshold Logic, IEEE Transactions on Computers, 49:3, (193-207), Online publication date: 1-Mar-2000.

Hiasat A (2000). New Efficient Structure for a Modular Multiplier for RNS, IEEE Transactions on Computers, 49:2, (170-174), Online publication date: 1-Feb-2000.

Anghel L and Nicolaidis M Cost reduction and evaluation of temporary faults detecting technique Proceedings of the conference on Design, automation and test in Europe, (591-598)

Um J, Kim T and Liu C Optimal allocation of carry-save-adders in arithmetic optimization Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (410-413)

Schwarz E and Krygowski C (2019). The S/390 G5 floating-point unit, IBM Journal of Research and Development, 43:5, (707-721), Online publication date: 1-Sep-1999.

Gizopoulos D, Paschalis A and Zorian Y (1999). An Effective Built-In Self-Test Scheme for Parallel Multipliers, IEEE Transactions on Computers, 48:9, (936-950), Online publication date: 1-Sep-1999.

Yurdakul A and Dündar G (2018). Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions, Journal of VLSI Signal Processing Systems, 22:3, (163-172), Online publication date: 1-Sep-1999.

Nicolaidis M and Duarte R (1999). Fault-Secure Parity Prediction Booth Multipliers, IEEE Design & Test, 16:3, (90-101), Online publication date: 1-Jul-1999.

Park S and Choi K Performance-driven scheduling with bit-level chaining Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (286-291)

Kollig P and Al-Hashimi B Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, (227-234)

Noufal I and Nicolaidis M A CAD framework for generating self-checking multipliers based on residue codes Proceedings of the conference on Design, automation and test in Europe, (29-es)

Kim T, Jao W and Tjiang S Arithmetic optimization using carry-save-adders Proceedings of the 35th annual Design Automation Conference, (433-438)

Stelling P, Martel C, Oklobdzija V and Ravi R (1998). Optimal Circuits for Parallel Multipliers, IEEE Transactions on Computers, 47:3, (273-285), Online publication date: 1-Mar-1998.

Duarte R, Nicolaidis M, Bederr H and Zorian Y (2019). Efficient Totally Self-Checking Shifter Design, Journal of Electronic Testing: Theory and Applications, 12:1-2, (29-39), Online publication date: 1-Feb-1998.

Jain J, Bitner J, Abadir M, Abraham J and Fussell D (1997). Indexed BDDs, IEEE Transactions on Computers, 46:11, (1230-1245), Online publication date: 1-Nov-1997.

Jacobson H and Gopalakrishnan G Asynchronous Microengines for Efficient High-level Control Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

Schwarz E, Sigal L and McPherson T (2019). CMOS floating-point unit for the S/390 parallel enterprise server G4, IBM Journal of Research and Development, 41:4-5, (475-488), Online publication date: 1-Jul-1997.

Nicolaidis M, Duarte R, Manich S and Figueras J (1997). Fault-Secure Parity Prediction Arithmetic Operators, IEEE Design & Test, 14:2, (60-71), Online publication date: 1-Apr-1997.

Duarte R, Nicolaidis M, Bederr H and Zorian Y Fault-secure shifter design Proceedings of the 1997 European conference on Design and Test

Mekhallalati M, Ashur A and Ibrahim M (2019). Novel Radix Finite Field Multiplier for GF(2m), Journal of VLSI Signal Processing Systems, 15:3, (233-245), Online publication date: 1-Mar-1997.

Mekhallalati M, Ashur A and Ibrahim M (2019). Novel Radix Finite Field Multiplier for GF(2 ^m ), Journal of VLSI Signal Processing Systems, 15:3, (233-245), Online publication date: 1-Mar-1997.

Lo J (1997). A Fast Binary Adder with Conditional Carry Generation, IEEE Transactions on Computers, 46:2, (248-253), Online publication date: 1-Feb-1997.

Lin R Shift Switching with Domino Logic Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Cheng F, Unger S, Theobald M and Cho W Delay-Insensitive Carry-Lookahead Adders Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hu Y and Chern H (1996). A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR), IEEE Transactions on Computers, 45:12, (1370-1378), Online publication date: 1-Dec-1996.

Schwarz E and Flynn M (1996). Hardware Starting Approximation Method and Its Application to the Square Root Operation, IEEE Transactions on Computers, 45:12, (1356-1369), Online publication date: 1-Dec-1996.

Ciminiera L and Montuschi P (1996). Carry-Save Multiplication Schemes Without Final Addition, IEEE Transactions on Computers, 45:9, (1050-1055), Online publication date: 1-Sep-1996.

Nicolaidis M, Manich S and Figueras J Achieving Fault Secureness in Parity Prediction Arithmetic Operators Proceedings of the 1996 European conference on Design and Test

Oklobdzija V, Villeger D and Liu S (1996). A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach, IEEE Transactions on Computers, 45:3, (294-306), Online publication date: 1-Mar-1996.

Poornaiah D and Mohan P A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Mandelbaum D and Mandelbaum S (1996). A Fast, Efficient Parallel-Acting Method of Generating Functions Defined by Power Series, Including Logarithm, Exponential, and Sine, Cosine, IEEE Transactions on Parallel and Distributed Systems, 7:1, (33-45), Online publication date: 1-Jan-1996.

Mandelbaum D (1995). Division Using a Logarithmic-Exponential Transform to Form a Short Reciprocal, IEEE Transactions on Computers, 44:11, (1326-1330), Online publication date: 1-Nov-1995.

Lee M, Tiwari V, Malik S and Fujita M Power analysis and low-power scheduling techniques for embedded DSP software Proceedings of the 8th international symposium on System synthesis, (110-115)

Williams T and Burgess N (1995). Choices of Operand Truncation in the SRT Division Algorithm, IEEE Transactions on Computers, 44:7, (933-938), Online publication date: 1-Jul-1995.

Lin M and Oruç A (1994). Constant Time Inner Product and Matrix Computations on Permutation Network Processors, IEEE Transactions on Computers, 43:12, (1429-1434), Online publication date: 1-Dec-1994.

Ercegovac M, Lang T and Montuschi P (2019). Very-High Radix Division with Prescaling and Selection by Rounding, IEEE Transactions on Computers, 43:8, (909-918), Online publication date: 1-Aug-1994.

Lo J (1994). Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands, IEEE Transactions on Computers, 43:4, (400-412), Online publication date: 1-Apr-1994.

Piestrak S (2019). Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders, IEEE Transactions on Computers, 43:1, (68-77), Online publication date: 1-Jan-1994.

Kabuo H, Taniguchi T, Miyoshi A, Yamashita H, Urano M, Edamatsu H and Kuninobu S (2019). Accurate Rounding Scheme for the Newton-Raphson Method Using Redundant Binary Representation, IEEE Transactions on Computers, 43:1, (43-51), Online publication date: 1-Jan-1994.

Kawahito S, Ishida M, Nakamura T, Kameyama M and Higuchi T (2019). High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits, IEEE Transactions on Computers, 43:1, (34-42), Online publication date: 1-Jan-1994.

Schwarz E and Flynn M (2019). Parallel High-Radix Nonrestoring Division, IEEE Transactions on Computers, 42:10, (1234-1246), Online publication date: 1-Oct-1993.

Awaga M and Takahashi H (2019). The μVP 64-Bit Vector Coprocessor, IEEE Micro, 13:5, (24-36), Online publication date: 1-Sep-1993.

Lo J, Thanawastien S and Rao T (2019). Berger Check Prediction for Array Multipliers and Array Dividers, IEEE Transactions on Computers, 42:7, (892-896), Online publication date: 1-Jul-1993.

Mandelbaum D (1993). Some Results on a SRT Type Division Scheme, IEEE Transactions on Computers, 42:1, (102-106), Online publication date: 1-Jan-1993.

Cortadella J and Llabería J (2019). Evaluation of A+B=K Conditions Without Carry Propagation, IEEE Transactions on Computers, 41:11, (1484-1488), Online publication date: 1-Nov-1992.

Lim Y (2019). Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications, IEEE Transactions on Computers, 41:10, (1333-1336), Online publication date: 1-Oct-1992.

Skavantzos A and Stouraitis T (2019). Decomposition of Complex Multipliers Using Polynomial Encoding, IEEE Transactions on Computers, 41:10, (1331-1333), Online publication date: 1-Oct-1992.

Scherson I, Kramer D and Alleyne B (2019). Bit-Parallel Arithmetic in a Massively-Parallel Associative Processor, IEEE Transactions on Computers, 41:10, (1201-1210), Online publication date: 1-Oct-1992.

Fagin B (2019). Fast Addition of Large Integers, IEEE Transactions on Computers, 41:9, (1069-1077), Online publication date: 1-Sep-1992.

Lang T and Montuschi P (2019). Higher Radix Square Root with Prescaling, IEEE Transactions on Computers, 41:8, (996-1009), Online publication date: 1-Aug-1992.

Sauerbrey J and Dietel A Resource requirements for the application of addition chains in modulo exponentiation Proceedings of the 11th annual international conference on Theory and application of cryptographic techniques, (174-182)

Singh G GRIP Proceedings of the 24th annual international symposium on Microarchitecture, (143-152)

Draper R An overview of supertoroidal networks Proceedings of the third annual ACM symposium on Parallel algorithms and architectures, (95-102)

Lyons K A fast method for finding an integer square root Proceedings of the second and third annual workshops on Forth, (27-30)

Singh U and Chen C A transistor reordering technique for gate matrix layout Proceedings of the 27th ACM/IEEE Design Automation Conference, (462-467)

Chatterjee A and Abraham J (1990). The Testability of Generalized Counters Under Multiple Faulty Cells, IEEE Transactions on Computers, 39:11, (1378-1385), Online publication date: 1-Nov-1990.

Carter T and Robertson J (2019). The Set Theory of Arithmetic Decomposition, IEEE Transactions on Computers, 39:8, (993-1005), Online publication date: 1-Aug-1990.

Hong S (1990). The Design of a Testable Parallel Multiplier, IEEE Transactions on Computers, 39:3, (411-416), Online publication date: 1-Mar-1990.

Mandelbaum D (2019). A Systematic Method for Division with High Average Bit Skipping, IEEE Transactions on Computers, 39:1, (127-130), Online publication date: 1-Jan-1990.

Lai J and Chao M Parallel algorithm and VLSI architecture for a robot's inverse kinematics Proceedings of the 1989 ACM/IEEE conference on Supercomputing, (123-132)

Boute R (2019). Representational and Denotational Semantics of Digital Systems, IEEE Transactions on Computers, 38:7, (986-999), Online publication date: 1-Jul-1989.

Milutinovic V, Bettinger M and Helbig W (2019). Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor, IEEE Transactions on Computers, 38:6, (874-880), Online publication date: 1-Jun-1989.

Dally W Micro-optimization of floating-point operations Proceedings of the third international conference on Architectural support for programming languages and operating systems, (283-289)

Dally W (1989). Micro-optimization of floating-point operations, ACM SIGARCH Computer Architecture News, 17:2, (283-289), Online publication date: 1-Apr-1989.

Vassiliadis S, Schwarz E and Hanrahan D (2019). A General Proof for Overlapped Multiple-Bit Scanning Multiplications, IEEE Transactions on Computers, 38:2, (172-183), Online publication date: 1-Feb-1989.

Zhang C, Shirazi B and Yun D Residue number conversion Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow, (390-396)

Wu I (1987). A Fast 1-D Serial-Parallel Systolic Multiplier, IEEE Transactions on Computers, 36:10, (1243-1247), Online publication date: 1-Oct-1987.

Parhami B (1987). On the Complexity of Table Lookup for Iterative Division, IEEE Transactions on Computers, 36:10, (1233-1236), Online publication date: 1-Oct-1987.

Guyot A, Hochet B and Muller J (1987). A Way to Build Efficient Carry-Skip Adders, IEEE Transactions on Computers, 36:10, (1144-1152), Online publication date: 1-Oct-1987.

Milutinovic V and Lopez-Benitez N (1987). A GaAs-Based Microprocessor Architecture for Real-Time Applications, IEEE Transactions on Computers, 36:6, (714-727), Online publication date: 1-Jun-1987.

Purdy C and Purdy G (1987). Integer Division in Linear Time with Bounded Fan-In, IEEE Transactions on Computers, 36:5, (640-644), Online publication date: 1-May-1987.

Zhang C, Shirazi B and Yun D Computing multiple modulo summation (abstract only) Proceedings of the 15th annual conference on Computer Science

Hurson A and Shirazi B A systolic multiplier unit and its VLSI design Proceedings of the 12th annual international symposium on Computer architecture, (302-309)

Bamji C, Hauck C and Allen J A design by example regular structure generator Proceedings of the 22nd ACM/IEEE Design Automation Conference, (16-22)

Hurson A and Shirazi B (1985). A systolic multiplier unit and its VLSI design, ACM SIGARCH Computer Architecture News, 13:3, (302-309), Online publication date: 1-Jun-1985.

Chu K and Sharma R A technology independent MOS multiplier generator Proceedings of the 21st Design Automation Conference, (90-97)

Shen J and Ferguson F (1984). The Design of Easily Testable VLSI Array Multipliers, IEEE Transactions on Computers, 33:6, (554-560), Online publication date: 1-Jun-1984.

Rhyne T (1984). Limitations on Carry Lookahead Networks, IEEE Transactions on Computers, 33:4, (373-374), Online publication date: 1-Apr-1984.

Bandeira N, Vaccaro K and Howard J (1983). A Two's Complement Array Multiplier Using True Values of the Operands, IEEE Transactions on Computers, 32:8, (745-747), Online publication date: 1-Aug-1983.

Blakely G (1983). A Computer Algorithm for Calculating the Product AB Modulo M, IEEE Transactions on Computers, 32:5, (497-500), Online publication date: 1-May-1983.

Kai Hwang and Yeng-Heng Cheng (1982). Partitioned Matrix Algorithms for VLSI Arithmetic Systems, IEEE Transactions on Computers, 31:12, (1215-1224), Online publication date: 1-Dec-1982.

Gerrity G (1982). Computer Representation of Real Numbers, IEEE Transactions on Computers, 31:8, (709-714), Online publication date: 1-Aug-1982.

Johnstone P Representational error in binary and decimal numbering systems Proceedings of the 20th annual ACM Southeast Regional Conference, (85-88)

Brent R and Kung H (1982). A Regular Layout for Parallel Adders, IEEE Transactions on Computers, 31:3, (260-264), Online publication date: 1-Mar-1982.

Bellon C, Liothin A, Sadier S, Saucier G, Velazco R, Grillot F and Issenman M Automatic generation of microprocessor test programs Proceedings of the 19th Design Automation Conference, (566-573)

Thayse A (1982). Synthesis and Optimization of Programs by Means of P-Functions, IEEE Transactions on Computers, 31:1, (34-40), Online publication date: 1-Jan-1982.

Irwin M and Heller D Online pipeline systems for recursive numeric computations Proceedings of the 7th annual symposium on Computer Architecture, (292-299)