Article

A Register File with Transposed Access Mode

ICCD '00: Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Page 559

Published: 17 September 2000 Publication History

Abstract

We introduce a new register file architecture that provides both row-wise and column-wise accesses, thus allowing partitioned instructions to be used in column-wise processing without transposition overhead. This feature can accelerate 2D separable image and video processing algorithms, such as 2D convolution and 2D discrete cosine transform (DCT), by eliminating the transposition steps.

References

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C. Basoglu, R. Gove, K. Kojima, and J. O'Donnell, "A single-chip processor for media applications: the MAP1000," International Journal of Imaging Systems and Technology, vol. 10, pp. 96-106, 1999.

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ICSL, http://icsl.ee.washington.edu/papers

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Shahbahrami AJuurlink BBorodin DVassiliadis S(2006)Avoiding conversion and rearrangement overhead in SIMD architecturesInternational Journal of Parallel Programming10.1007/s10766-006-0015-034:3(237-260)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1007/s10766-006-0015-0
Shahbahrami AJuurlink BVassiliadis SBagherzadeh NValero MRamirez A(2005)Matrix register file and extended subwordsProceedings of the 2nd conference on Computing frontiers10.1145/1062261.1062291(171-179)Online publication date: 4-May-2005
https://dl.acm.org/doi/10.1145/1062261.1062291
Tanskanen JNiittylahti J(2004)Scalable Parallel Memory Architectures for Video CodingJournal of VLSI Signal Processing Systems10.1023/B:VLSI.0000040428.04740.fe38:2(173-199)Online publication date: 1-Sep-2004
https://dl.acm.org/doi/10.1023/B%3AVLSI.0000040428.04740.fe

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ICCD '00: Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

September 2000

ISBN:0769508014

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IEEE Computer Society

United States

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Published: 17 September 2000

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Shahbahrami AJuurlink BBorodin DVassiliadis S(2006)Avoiding conversion and rearrangement overhead in SIMD architecturesInternational Journal of Parallel Programming10.1007/s10766-006-0015-034:3(237-260)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1007/s10766-006-0015-0
Shahbahrami AJuurlink BVassiliadis SBagherzadeh NValero MRamirez A(2005)Matrix register file and extended subwordsProceedings of the 2nd conference on Computing frontiers10.1145/1062261.1062291(171-179)Online publication date: 4-May-2005
https://dl.acm.org/doi/10.1145/1062261.1062291
Tanskanen JNiittylahti J(2004)Scalable Parallel Memory Architectures for Video CodingJournal of VLSI Signal Processing Systems10.1023/B:VLSI.0000040428.04740.fe38:2(173-199)Online publication date: 1-Sep-2004
https://dl.acm.org/doi/10.1023/B%3AVLSI.0000040428.04740.fe

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Register file partitioning and recompilation for register file power reduction

Multiple-banked register file architectures

Register Allocation for Banked Register File

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