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A timing-constrained algorithm for simultaneous global routing of multiple nets

Authors:

Sachin S. SapatnekarAuthors Info & Claims

ICCAD '00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Pages 99 - 103

Published: 05 November 2000 Publication History

Abstract

In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities under timing constraints. These flexibilities are exploited for congestion reduction through a network flow based hierarchical bisection and assignment process. Experimental results on benchmark circuits are quite promising.

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Cited By

Tu PPui CYoung EChen DHomayoun HTaskin B(2018)Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based AccelerationProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194556(261-266)Online publication date: 30-May-2018
https://dl.acm.org/doi/10.1145/3194554.3194556
Huang HChang SLin YHsieh T(2009)Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architectureProceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems10.5555/1576594.1576601(31-34)Online publication date: 20-May-2009
https://dl.acm.org/doi/10.5555/1576594.1576601
Cho MLu KYuan KPan D(2009)BoxRouter 2.0ACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149757514:2(1-21)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497575
Show More Cited By

A timing-constrained algorithm for simultaneous global routing of multiple nets
1. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
2. Theory of computation
  1. Design and analysis of algorithms
    1. Graph algorithms analysis

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cover image ACM Conferences

ICCAD '00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

November 2000

558 pages

ISBN:0780364481

Conference Chair:
Ellen M. Sentovich
Cadence Berkley Labs., Berkley, California

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SIGDA: ACM Special Interest Group on Design Automation
IEEE Circuits & Systems Society
The IEEE Computer Society DATC

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IEEE Press

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Published: 05 November 2000

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ICCAD '00

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SIGDA

ICCAD '00: International Conference on Computer Aided Design

November 5 - 9, 2000

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Tu PPui CYoung EChen DHomayoun HTaskin B(2018)Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based AccelerationProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194556(261-266)Online publication date: 30-May-2018
https://dl.acm.org/doi/10.1145/3194554.3194556
Huang HChang SLin YHsieh T(2009)Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architectureProceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems10.5555/1576594.1576601(31-34)Online publication date: 20-May-2009
https://dl.acm.org/doi/10.5555/1576594.1576601
Cho MLu KYuan KPan D(2009)BoxRouter 2.0ACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149757514:2(1-21)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497575
Yan J(2008)Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstructionACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442213:2(1-18)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344422
Cho MLu KYuan KPan DGielen G(2007)BoxRouter 2.0Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326176(503-508)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326176
Cho MPan DXiang HPuri RHassoun S(2006)Wire density driven global routing for CMP variation and timingProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233599(487-492)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233599
Cho MPan DSentovich E(2006)BoxRouterProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147009(373-378)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147009
Fang JLin IYuh PChang YWang J(2005)A routing algorithm for flip-chip designProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129708(753-758)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129708
Kubo YMiyashita HKajitani YTateishi K(2005)Equidistance routing in high-speed VLSI layout designIntegration, the VLSI Journal10.5555/1062115.171208438:3(439-449)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.5555/1062115.1712084
Xiong JHe L(2004)Full-Chip Multilevel Routing for Power and Signal IntegrityProceedings of the conference on Design, automation and test in Europe - Volume 210.5555/968879.969137Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968879.969137
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