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Can User-Level Protocols Take Advantage of Multi-CPU NICs?

Published: 15 April 2002 Publication History
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  • Abstract

    User-level protocols and their implementations on programmable network interface cards (NICs) have been alleviating the communication bottleneck for high speed interconnects. Most of the user-level protocols developed so far have been based on single-CPU NICs. One of the more popular current generation Gigabit Ethernet NICs includes two CPUs, though. This raises an open challenge whether performance of user-level protocols can be improved by taking advantage of a multi-CPU NIC. In this paper, we analyze the intrinsic issues associated with such a challenge and explore different parallelization and pipelining schemes to enhance the performance of our earlier developed EMP protocol for single-CPU Alteon NICs. Performance evaluation results indicate that parallelizing the receive path of the protocol can deliver 964 Mbps of bandwidth, close to the maximum achievable on Gigabit Ethernet. This scheme also delivers up to 8% improvement in latency for a range of message sizes. Parallelizing the send path leads to 17% improvement in bidirectional bandwidth.

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    Cited By

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    • (2007)RiceNICProceedings of the 2007 workshop on Experimental computer science10.1145/1281700.1281721(21-es)Online publication date: 13-Jun-2007
    • (2005)Addressing data compatibility on programmable network platformsProceedings of the 2005 ACM symposium on Architecture for networking and communications systems10.1145/1095890.1095908(125-134)Online publication date: 26-Oct-2005
    • (2005)Platform OverlaysProceedings of the international workshop on Network and operating systems support for digital audio and video10.1145/1065983.1066022(171-176)Online publication date: 13-Jun-2005
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        cover image Guide Proceedings
        IPDPS '02: Proceedings of the 16th International Parallel and Distributed Processing Symposium
        April 2002
        ISBN:0769515738

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        IEEE Computer Society

        United States

        Publication History

        Published: 15 April 2002

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        View all
        • (2007)RiceNICProceedings of the 2007 workshop on Experimental computer science10.1145/1281700.1281721(21-es)Online publication date: 13-Jun-2007
        • (2005)Addressing data compatibility on programmable network platformsProceedings of the 2005 ACM symposium on Architecture for networking and communications systems10.1145/1095890.1095908(125-134)Online publication date: 26-Oct-2005
        • (2005)Platform OverlaysProceedings of the international workshop on Network and operating systems support for digital audio and video10.1145/1065983.1066022(171-176)Online publication date: 13-Jun-2005
        • (2004)Comparing Ethernet and Myrinet for MPI communicationProceedings of the 7th workshop on Workshop on languages, compilers, and run-time support for scalable systems10.1145/1066650.1066659(1-7)Online publication date: 22-Oct-2004
        • (2003)Exploiting task-level concurrency in a programmable network interfaceACM SIGPLAN Notices10.1145/966049.78150638:10(61-72)Online publication date: 11-Jun-2003
        • (2003)Exploiting task-level concurrency in a programmable network interfaceProceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming10.1145/781498.781506(61-72)Online publication date: 11-Jun-2003
        • (2003)A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NICProceedings of the 2003 ACM/IEEE conference on Supercomputing10.1145/1048935.1050173Online publication date: 15-Nov-2003

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