Article

Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking

Authors:

Miroslav N. Velev,

Randal E. BryantAuthors Info & Claims

FMCAD '98: Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

Pages 18 - 35

Published: 04 November 1998 Publication History

Abstract

We present a way to abstract functional units in symbolic simulation of actual circuits, thus achieving the effect of uninterpreted functions at the bit-level. Additionally, we propose an efficient encoding technique that can be used to represent uninterpreted symbols with BDDs, while allowing these symbols to be propagated by simulation with a conventional bit-level symbolic simulator. Our abstraction and encoding techniques result in an automatic symmetry reduction and allow the control and forwarding logic of the actual circuit to be used unmodified. The abstraction method builds on the behavioral Efficient Memory Model [18][19] and its capability to dynamically introduce consistent initial state, which is identical for two simulation sequences. We apply the abstraction and encoding ideas on the verification of pipelined microprocessors by correspondence checking, where a pipelined microprocessor is compared against a non-pipelined specification.

References

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Cited By

Srinivasan SKatti RBjesse PSlobodová A(2011)DesynchronizationProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157687(215-222)Online publication date: 30-Oct-2011
https://dl.acm.org/doi/10.5555/2157654.2157687
Velev MGao PPhillips JHu AGraeb H(2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132476
Velev MGao P(2011)Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional unitsProceedings of the 13th international conference on Formal methods and software engineering10.5555/2075089.2075117(307-322)Online publication date: 26-Oct-2011
https://dl.acm.org/doi/10.5555/2075089.2075117
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cover image Guide Proceedings

FMCAD '98: Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

November 1998

529 pages

ISBN:3540651918

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 04 November 1998

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Cited By

Srinivasan SKatti RBjesse PSlobodová A(2011)DesynchronizationProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157687(215-222)Online publication date: 30-Oct-2011
https://dl.acm.org/doi/10.5555/2157654.2157687
Velev MGao PPhillips JHu AGraeb H(2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132476
Velev MGao P(2011)Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional unitsProceedings of the 13th international conference on Formal methods and software engineering10.5555/2075089.2075117(307-322)Online publication date: 26-Oct-2011
https://dl.acm.org/doi/10.5555/2075089.2075117
Velev MGao P(2011)Automatic formal verification of reconfigurable DSPsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950881(293-296)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950881
Velev MGao P(2010)Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessorsProceedings of the 12th international conference on Formal engineering methods and software engineering10.5555/1939864.1939894(355-370)Online publication date: 17-Nov-2010
https://dl.acm.org/doi/10.5555/1939864.1939894
Velev M(2006)Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value PredictionProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.142(51-56)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.142
Velev M(2004)Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of MicroprocessorsProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969033Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.969033
Sawada JHunt W(2002)Verification of FM9801Formal Methods in System Design10.1023/A:101412263027720:2(187-222)Online publication date: 1-Mar-2002
https://dl.acm.org/doi/10.1023/A%3A1014122630277
Bryant RGerman SVelev M(2001)Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logicACM Transactions on Computational Logic10.1145/371282.3713642:1(93-134)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.1145/371282.371364
Velev MBryant RDe Micheli G(2000)Formal verification of superscale microprocessors with multicycle functional units, exception, and branch predictionProceedings of the 37th Annual Design Automation Conference10.1145/337292.337331(112-117)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337331
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