Article

Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic

Authors:

Miroslav N. Velev,

Randal E. BryantAuthors Info & Claims

CHARME '99: Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

Pages 37 - 53

Published: 27 September 1999 Publication History

Abstract

We present a collection of ideas that allows the pipeline verification method pioneered by Burch and Dill [5] to scale very efficiently to dual-issue superscalar processors. We achieve a significant speedup in the verification of such processors, compared to the result by Burch [6], while using an entirely automatic tool. Instrumental to our success are exploiting the properties of positive equality [3][4] and the simplification capabilities of BDDs.

References

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R.E. Bryant, S. German, and M.N. Velev, "Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions,"² Computer-Aided Verification (CAV'99), LNCS, Springer-Verlag, June 1999.

[4]

R.E. Bryant, S. German, and M.N. Velev, "Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic,"² Technical Report CMU-CS-99-115, Carnegie Mellon University, 1999.

[5]

J.R. Burch, and D.L. Dill, "Automated Verification of Pipelined Microprocessor Control," Computer-Aided Verification (CAV'94), D.L. Dill, ed., LNCS 818, Springer-Verlag, June 1994, pp. 68-80. Available from: http://sprout.stanford.edu/papers.html.

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J.R. Burch, "Techniques for Verifying Superscalar Microprocessors," 33rd Design Automation Conference (DAC'96), June 1996, pp. 552-557.

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CUDD-2.3.0, URL: http://vlsi.colorado.edu/~fabio.

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A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal, "BDD Based Procedures for a Theory of Equality with Uninterpreted Functions," Computer-Aided Verification (CAV'98), A.J. Hu and M.Y. Vardi, eds., LNCS 1427, Springer-Verlag, June 1998, pp. 244-255.

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GRASP, URL: http://andante.eecs.umich.edu.

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A.J. Isles, R. Hojati, and R.K. Brayton, "Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory," Computer-Aided Verification (CAV98), A.J. Hu and M.Y. Vardi, eds., LNCS 1427, Springer-Verlag, June 1998, pp. 256-267.

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J.P. Marques-Silva, and K.A. Sakallah, "GRASP: A Search Algorithm for Propositional Satisfiability," IEEE Transactions on Computers, Vol. 48, No. 5, May 1999, pp. 506-521.

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A. Pnueli, Y. Rodeh, O. Shtrichman, and M. Siegel, "Deciding Equality Formulas by Small-Domain Instantiations," Computer-Aided Verification (CAV'99), LNCS, Springer-Verlag, June 1999.

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G. Stålmarck, "A System for Determining Propositional Logic Theorems by Applying Values and Rules to Triplets that are Generated from a Formula", Swedish Patent No. 467 076 (approved 1992), U.S. Patent No. 5 276 897 (1994), European Patent No. 0403 454 (1995), 1989.

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Stanford Validity Checker (SVC), URL: http://sprout.Stanford.EDU/SVC.

[18]

M.N. Velev, and R.E. Bryant, "Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation,"² International Conference on Application of Concurrency to System Design (CSD'98), IEEE Computer Society, March 1998, pp. 200-212.

[19]

M.N. Velev, and R.E. Bryant, "Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking,"² Formal Methods in Computer-Aided Design (FMCAD'98), G. Gopalakrishnan and P. Windley, eds., LNCS 1522, Springer-Verlag, November 1998, pp. 18-35.

[20]

M.N. Velev, and R.E. Bryant, "Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors,"² 36th Design Automation Conference (DAC'99), June 1999, pp. 397-401.

[21]

P.J. Windley, and J.R. Burch, "Mechanically Checking a Lemma Used in an Automatic Verification Tool," Formal Methods in Computer-Aided Design (FMCAD'96), M. Srivas and A. Camilleri, eds., LNCS 1166, Springer-Verlag, November 1996, pp. 362-376.

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Cited By

Velev MGao PChang Y(2014)Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for boolean encoding of cardinalityProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691502(676-683)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691502
Srinivasan SKatti RBjesse PSlobodová A(2011)DesynchronizationProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157687(215-222)Online publication date: 30-Oct-2011
https://dl.acm.org/doi/10.5555/2157654.2157687
Velev MGao PPhillips JHu AGraeb H(2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132476
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Index Terms

Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic
1. Theory of computation
  1. Logic

Index terms have been assigned to the content through auto-classification.

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cover image Guide Proceedings

CHARME '99: Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

September 1999

364 pages

ISBN:3540665595

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 27 September 1999

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Cited By

Velev MGao PChang Y(2014)Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for boolean encoding of cardinalityProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691502(676-683)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691502
Srinivasan SKatti RBjesse PSlobodová A(2011)DesynchronizationProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157687(215-222)Online publication date: 30-Oct-2011
https://dl.acm.org/doi/10.5555/2157654.2157687
Velev MGao PPhillips JHu AGraeb H(2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132476
Velev MGao P(2011)Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional unitsProceedings of the 13th international conference on Formal methods and software engineering10.5555/2075089.2075117(307-322)Online publication date: 26-Oct-2011
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Velev MGao P(2011)Automatic formal verification of reconfigurable DSPsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950881(293-296)Online publication date: 25-Jan-2011
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Velev MGao P(2010)Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessorsProceedings of the 12th international conference on Formal engineering methods and software engineering10.5555/1939864.1939894(355-370)Online publication date: 17-Nov-2010
https://dl.acm.org/doi/10.5555/1939864.1939894
Velev MGao PLin Y(2010)A method for debugging of pipelined processors in formal verification by correspondence checkingProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899866(619-624)Online publication date: 18-Jan-2010
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Järvisalo MJunttila T(2009)Limitations of restricted branching in clause learningConstraints10.1007/s10601-008-9062-z14:3(325-356)Online publication date: 1-Sep-2009
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Järvisalo MJunttila T(2007)Limitations of restricted branching in clause learningProceedings of the 13th international conference on Principles and practice of constraint programming10.5555/1771668.1771697(348-363)Online publication date: 23-Sep-2007
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Beyer SJacobi CKröning DLeinenbach DPaul W(2006)Putting it all together --- Formal verification of the VAMPInternational Journal on Software Tools for Technology Transfer (STTT)10.5555/2990015.32209428:4-5(411-430)Online publication date: 1-Aug-2006
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