Article

Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation

Author:

Charles HymansAuthors Info & Claims

SAS '02: Proceedings of the 9th International Symposium on Static Analysis

Pages 444 - 460

Published: 17 September 2002 Publication History

Abstract

We are interested in the automatic verification of digital designs specified in the popular hardware description language VHDL. This paper presents a static analysis that computes a superset of the states maybe reached during the simulation of a VHDL design. We follow the methodology of abstract interpretation. To model the execution of a VHDL description, we first define a concise structural operational semantics. Our analysis is then derived by abstraction from this formal model. It is designed so as to be parametric in the representation of sets of states. Hence, trade-offs between cost and precision can be made by plugging in different abstract domains. This is of particular importance in the case of hardware verification, where one of the major obstacle to the integration of automatic tools in the design flow is the state-explosion problem they face. We instantiate our analysis with a domain that consists in a collection of vectors of constants and whose size is linear in the size of the unit under verification. Among other things, our analysis allows us to assert safety properties.

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Cited By

Li XTiwari MOberg JKashyap VChong FSherwood THardekopf BHall MPadua D(2011)CaissonProceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/1993498.1993512(109-120)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/1993498.1993512
Li XTiwari MOberg JKashyap VChong FSherwood THardekopf B(2011)CaissonACM SIGPLAN Notices10.1145/1993316.199351246:6(109-120)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/1993316.1993512
Li XTiwari MHardekopf BSherwood TChong FBanerjee AGarg D(2010)Secure information flow analysis for hardware designProceedings of the 5th ACM SIGPLAN Workshop on Programming Languages and Analysis for Security10.1145/1814217.1814225(1-7)Online publication date: 10-Jun-2010
https://dl.acm.org/doi/10.1145/1814217.1814225
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cover image Guide Proceedings

SAS '02: Proceedings of the 9th International Symposium on Static Analysis

September 2002

525 pages

ISBN:3540442359

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 17 September 2002

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Cited By

Li XTiwari MOberg JKashyap VChong FSherwood THardekopf BHall MPadua D(2011)CaissonProceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/1993498.1993512(109-120)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/1993498.1993512
Li XTiwari MOberg JKashyap VChong FSherwood THardekopf B(2011)CaissonACM SIGPLAN Notices10.1145/1993316.199351246:6(109-120)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/1993316.1993512
Li XTiwari MHardekopf BSherwood TChong FBanerjee AGarg D(2010)Secure information flow analysis for hardware designProceedings of the 5th ACM SIGPLAN Workshop on Programming Languages and Analysis for Security10.1145/1814217.1814225(1-7)Online publication date: 10-Jun-2010
https://dl.acm.org/doi/10.1145/1814217.1814225
Thesing SMin SYi W(2006)Modeling a system controller for timing analysisProceedings of the 6th ACM & IEEE International conference on Embedded software10.1145/1176887.1176929(292-300)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176887.1176929
Thompson SMycroft AHatcliff JTip F(2006)Bit-level partial evaluation of synchronous circuitsProceedings of the 2006 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation10.1145/1111542.1111548(29-37)Online publication date: 9-Jan-2006
https://dl.acm.org/doi/10.1145/1111542.1111548
Hymans C(2005)Verification of an error correcting code by abstract interpretationProceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation10.1007/978-3-540-30579-8_22(330-345)Online publication date: 17-Jan-2005
https://dl.acm.org/doi/10.1007/978-3-540-30579-8_22
Tolstrup TNielson FNielson H(2005)Information flow analysis for VHDLProceedings of the 8th international conference on Parallel Computing Technologies10.1007/11535294_8(79-98)Online publication date: 5-Sep-2005
https://dl.acm.org/doi/10.1007/11535294_8

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