Article

Test Pattern Generation for Realistic Bridge Faults in CMOS ICs

Authors:

F. Joel Ferguson,

Tracy LarrabeeAuthors Info & Claims

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner

Pages 492 - 499

Published: 26 October 1991 Publication History

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Yang FChakravarty SDevta-Prasanna NReddy SPomeranz IWakabayashi K(2009)Detectability of internal bridging faults in scan chainsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509787(678-683)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509787
Engelke PBecker BRenovell MSchloeffel JBraitling BPolian I(2009)SUPERBACM Transactions on Design Automation of Electronic Systems10.1145/1562514.159683114:4(1-21)Online publication date: 28-Aug-2009
https://dl.acm.org/doi/10.1145/1562514.1596831
Engelke PPolian ISchloeffel JBecker BSciuto D(2008)Resistive bridging fault simulation of industrial circuitsProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403527(628-633)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403527
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Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
1. Hardware

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Automatic Test Pattern Generation for Resistive Bridging Faults

An ATPG for resistive bridging faults in combinational or full-scan circuits is proposed. It combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle static effects ...

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Published In

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner

October 1991

1086 pages

ISBN:0818691565

Publisher

IEEE Computer Society

United States

Publication History

Published: 26 October 1991

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Yang FChakravarty SDevta-Prasanna NReddy SPomeranz IWakabayashi K(2009)Detectability of internal bridging faults in scan chainsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509787(678-683)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509787
Engelke PBecker BRenovell MSchloeffel JBraitling BPolian I(2009)SUPERBACM Transactions on Design Automation of Electronic Systems10.1145/1562514.159683114:4(1-21)Online publication date: 28-Aug-2009
https://dl.acm.org/doi/10.1145/1562514.1596831
Engelke PPolian ISchloeffel JBecker BSciuto D(2008)Resistive bridging fault simulation of industrial circuitsProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403527(628-633)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403527
Polian IEngelke PRenovell MBecker B(2005)Modeling Feedback Bridging Faults with Non-Zero ResistanceJournal of Electronic Testing: Theory and Applications10.1007/s10836-005-5287-621:1(57-69)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1007/s10836-005-5287-6
Krishnaswamy VMa AVishakantaiah P(2001)A Study of Bridging Defect Probabilities on a Pentium (tm) 4 CPUProceedings of the 2001 IEEE International Test Conference10.5555/839296.843846Online publication date: 30-Oct-2001
https://dl.acm.org/doi/10.5555/839296.843846
Shaw DAl-Khalili DRozon CErnst R(2001)Accurate CMOS bridge fault modeling with neural network-based VHDL saboteursProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603204(531-536)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603204
Rearick JMaxwell P(2000)Deception by DesignProceedings of the 2000 IEEE International Test Conference10.5555/839295.843592Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843592
Stroud CEmmert JBailey JChhor KNikolic D(2000)Bridging Fault Extraction from Physical Design Data for Manufacturing Test DevelopmentProceedings of the 2000 IEEE International Test Conference10.5555/839295.843566Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843566
Maeda TKinoshita K(2000)Precise Test Generation for Resistive Bridging Faults of CMOS Combinational CircuitsProceedings of the 2000 IEEE International Test Conference10.5555/839295.843558Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843558
Grimaila MLee SDworak JButler KStewart BBalachandran HHouchins BMathur VPark JWang LMercer M(1999)REDO - Probabilistic Excitation and Deterministic Observation - First Commercial ExperimentProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836541Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836541
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TEST PATTERN GENERATION FOR REALISTIC BRIDGE FAULTS IN CMOS ICs

Intrinsic leakage in deep submicron CMOS ICs—measurement-based test solutions

Automatic Test Pattern Generation for Resistive Bridging Faults

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