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AMLETO: a multi-language environment for functional test generation

Published: 30 October 2001 Publication History

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  • (2019)An extensive evaluation of search-based software testingSoft Computing - A Fusion of Foundations, Methodologies and Applications10.1007/s00500-017-2906-y23:6(1933-1946)Online publication date: 1-Mar-2019
  • (2016)Combining graph-based guidance with error effect simulation for efficient safety analysisProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972072(1132-1135)Online publication date: 14-Mar-2016
  • (2014)System-level reliability exploration framework for heterogeneous MPSoCProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591519(9-14)Online publication date: 20-May-2014
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cover image Guide Proceedings
Proceedings of the IEEE International Test Conference 2001
October 2001
1170 pages
ISBN:0780371690

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IEEE Computer Society

United States

Publication History

Published: 30 October 2001

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Cited By

View all
  • (2019)An extensive evaluation of search-based software testingSoft Computing - A Fusion of Foundations, Methodologies and Applications10.1007/s00500-017-2906-y23:6(1933-1946)Online publication date: 1-Mar-2019
  • (2016)Combining graph-based guidance with error effect simulation for efficient safety analysisProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972072(1132-1135)Online publication date: 14-Mar-2016
  • (2014)System-level reliability exploration framework for heterogeneous MPSoCProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591519(9-14)Online publication date: 20-May-2014
  • (2007)Properties Incompleteness Evaluation by Functional VerificationIEEE Transactions on Computers10.1109/TC.2007.101256:4(528-544)Online publication date: 1-Apr-2007
  • (2005)Logic-level mapping of high-level faultsIntegration, the VLSI Journal10.5555/1062115.171208338:3(467-490)Online publication date: 1-Jan-2005
  • (2005)Priority directed test generation for functional verification using neural networksProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120822(1052-1055)Online publication date: 18-Jan-2005
  • (2004)Logic-level analysis of high-level faultsProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.988977(100-103)Online publication date: 26-Apr-2004
  • (2003)Mixing ATPG and property checking for testing HW/SW interfacesProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764887(303-306)Online publication date: 28-Apr-2003
  • (2002)Protected IP-core test generationProceedings of the 12th ACM Great Lakes symposium on VLSI10.1145/505306.505320(59-64)Online publication date: 18-Apr-2002
  • (2002)An error simulation based approach to measure error coverage of formal propertiesProceedings of the 12th ACM Great Lakes symposium on VLSI10.1145/505306.505319(53-58)Online publication date: 18-Apr-2002

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