Article

A ROMless LFSR Reseeding Scheme for Scan-based BIST

Authors:

E. Kalligeros,

X. Kavousianos,

D. NikolosAuthors Info & Claims

ATS '02: Proceedings of the 11th Asian Test Symposium

Page 206

Published: 18 November 2002 Publication History

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Abstract

In this paper we present a new LFSR reseedling scheme for scan-based BIT suitable for circuits with random-pattern-resistant faults.The proposed scheme eliminates the need of a ROM for storing the seeds since the reseedings are performed dynamically by inverting some selected bits of the LFSR register.A time-to-market efficient algorithm is also presented for selecting the reseeding points in the test sequence, as well as a proper seed at each point.This algorithm targets complete fault coverage and minimization of the resulting test length and hardware overhead.Experimental results on ISCAS '85 and ISCAS '89 benchmark circuits demonstrate the advantages of this new LFSR reseeding approach in terms of area overhead and test application time.

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Song DKang S(2005)Increasing embedding probabilities of RPRPs in RIN based BISTProceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11572961_49(600-613)Online publication date: 24-Oct-2005
https://dl.acm.org/doi/10.1007/11572961_49
Zeng GIto H(2004)Hybrid BIST for System-on-a-Chip Using an Embedded FPGA CoreProceedings of the 22nd IEEE VLSI Test Symposium10.5555/987684.987958Online publication date: 25-Apr-2004
https://dl.acm.org/doi/10.5555/987684.987958
Kalligeros EKavousianos XNikolos DStan MGarrett DNakajima K(2003)A highly regular multi-phase reseeding technique for scan-based BISTProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764885(295-298)Online publication date: 28-Apr-2003
https://dl.acm.org/doi/10.1145/764808.764885

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LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test

This paper presents a new low-power test-data-compression scheme based on linear feedback shift register (LFSR) reseeding. A drawback of compression schemes based on LFSR reseeding is that the unspecified bits are filled with random values, which ...
LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs

Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression ...

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Published In

ATS '02: Proceedings of the 11th Asian Test Symposium

November 2002

ISBN:0769518257

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IEEE Computer Society

United States

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Published: 18 November 2002

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Song DKang S(2005)Increasing embedding probabilities of RPRPs in RIN based BISTProceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11572961_49(600-613)Online publication date: 24-Oct-2005
https://dl.acm.org/doi/10.1007/11572961_49
Zeng GIto H(2004)Hybrid BIST for System-on-a-Chip Using an Embedded FPGA CoreProceedings of the 22nd IEEE VLSI Test Symposium10.5555/987684.987958Online publication date: 25-Apr-2004
https://dl.acm.org/doi/10.5555/987684.987958
Kalligeros EKavousianos XNikolos DStan MGarrett DNakajima K(2003)A highly regular multi-phase reseeding technique for scan-based BISTProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764885(295-298)Online publication date: 28-Apr-2003
https://dl.acm.org/doi/10.1145/764808.764885

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Recommendations

Efficient LFSR Reseeding Based on Internal-Response Feedback

LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test

LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs

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