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Inductance Analysis of On-Chip Interconnects

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S. Kundu,

U. GhoshalAuthors Info & Claims

EDTC '97: Proceedings of the 1997 European conference on Design and Test

Page 252

Published: 17 March 1997 Publication History

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Abstract

It is generally believed that inductance analysis of on-chip interconnect becomes important when the clock frequency of circuits rises above GHz level. In this paper we show that this perception is not true. It becomes necessary to consider the inductive effects in all circuits implemented in deep submicron CMOS technologies. For 0.25 /spl mu/m (lithography) technologies, where the supply voltage is expected to be in the range of 1.2-1.8 V, inductive effects are an important consideration regardless of system frequency. Furthermore, contrary to the popular belief we show that inductive effects are important even for highly resistive lines.

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Deschacht DServel GHuret FPaleczny EKennis PStroobandt DChristie PKahng A(2000)Theoretical limits for signal reflections due to inductance for on-chip interconnectionsProceedings of the 2000 international workshop on System-level interconnect prediction10.1145/333032.333033(55-60)Online publication date: 8-Apr-2000
https://dl.acm.org/doi/10.1145/333032.333033
Cuviello MDey SBai XZhao YWhite JSentovich E(1999)Fault modeling and simulation for crosstalk in system-on-chip interconnectsProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.340030(297-303)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.340030

Inductance Analysis of On-Chip Interconnects
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EDTC '97: Proceedings of the 1997 European conference on Design and Test

March 1997

596 pages

ISBN:0818677864

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IEEE Computer Society

United States

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Published: 17 March 1997

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EDTC96: European Design and Test Conference

March 17 - 20, 1997

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Deschacht DServel GHuret FPaleczny EKennis PStroobandt DChristie PKahng A(2000)Theoretical limits for signal reflections due to inductance for on-chip interconnectionsProceedings of the 2000 international workshop on System-level interconnect prediction10.1145/333032.333033(55-60)Online publication date: 8-Apr-2000
https://dl.acm.org/doi/10.1145/333032.333033
Cuviello MDey SBai XZhao YWhite JSentovich E(1999)Fault modeling and simulation for crosstalk in system-on-chip interconnectsProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.340030(297-303)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.340030

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Analysis of on-chip inductance effects for distributed RLC interconnects

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Analysis of on-chip inductance effects for distributed RLC interconnects

Trends of Key Advanced Device Technologies

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