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Architectural Exploration and Optimization for Counter Based Hardware Address Generation

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H. de ManAuthors Info & Claims

EDTC '97: Proceedings of the 1997 European conference on Design and Test

Page 293

Published: 17 March 1997 Publication History

Abstract

A set of automated system level techniques is presented for architectural exploration and optimization of counter based address generation units in real time signal processing systems. The goal is to explore different architectural alternatives available when mapping array references in order to select the most promising ones in area cost. The techniques are demonstrated on realistic test-vehicles, showing that architectural decision at early stages of the design process, can have a very large impact on the resulting area figure.

References

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{2} Texas Instruments. TMS320C5x User's Guide, 1993.

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{3} C. Liem, P. Paulin, and A. Jerraya. Address calculation for retargetable compilation and exploration of instruction-set architectures. In Proc. 33rd. ACM/IEEE Design Automation Conf., pages 597-600, 1996.

Digital Library

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{4} G. Araujo, A. Sudarsanam, and S. Malik. Instruction set design and optimizations for address computation in DSP architectures. In em Proc. 9th ACM/IEEE Intl. Symp. System Synthesis, pages 102-107, 1996.

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{5} S. Wuytack, F. Catthoor, L. Nachtergaele, and H. De Man. Power exploration for data dominated video applications. IEEE Intl. Symp. on Low Power Design, 1996.

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{6} P. Lippens, J. Van Meerbergen, A. Van der Werf, W. Verhaegh, B. McSweeney, J. Huisken, and O. McArdle. Phideo: A silicon compiler for high speed algorithms. In Proc. 2nd ACM/IEEE Europ. Design Automation Conf., pages 436-441, 1991.

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{7} M. Miranda, F. Catthoor, and H. De Man. Address equation multiplexing for real time signal processing applications. In VLSI Signal Processing, VII, pages 188-197, New York, 1994. J. Rabaey, P. Chau and J. Eldon (eds.). IEEE Press.

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{8} M. Miranda, F. Catthoor, M. Janssen and H. De Man. ADOPT: Efficient hardware address generation in distributed memory architectures. In Proc. 9th ACM/IEEE Intl. Symp. System Synthesis, pages 20-25, 1996.

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{9} D. Grant and P. Denyer. Address generation for array access based on modulus m counters. In Proc. 2nd ACM/IEEE Europ. Design Automation Conf., pages 118- 122, 1991.

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{10} D. Grant, J. Van Meerbergen, and P. Lippens. Optimization of address generator hardware. In Proc. 5th ACM/IEEE Europ. Design and Test Conf., pages 325-329, 1994.

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{11} B. Vanhoof, I. Bolsens, S. De Troth, L. Philips, J. Vanhoof, and H. De Man. Design of a voice coder with the cathedral-II silicon compiler. In Proc. of the User Forum and Euro ASIC prizes, EDAC-Euro ASIC-93, pages 150-153, 1993.

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{12} W. Geurts, F. Catthoor, and H. De Man. Time constrained allocation and assignment techniques for high throughput signal processing. In Proc. 29th ACM/IEEE Design Automation Conf., pages 124-127, Anaheim, CA, June 1993.

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{13} S. Note, W. Geurts, F. Catthoor, and H. De Man. Cathedral-III: Architecture driven high-level synthesis for high throughput DSP applications. In Proc. 28th ACM/IEEE Design Automation Conf., pages 597-602, 1991.

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{14} J.M. Janssen, F. Catthoor, and H. De Man. A specification invariant technique for operation cost minimization in flow-graphs. In 7th ACM/IEEE International Symposium on High-level Synthesis, pages 146-157, 1994.

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{15} S. Vernalde, P. Schaumont, I. Bolsens, and H. De Man. Synthesis of high throughput DSP ASICs using application specific data-paths. DSP & Multimedia Technology, 3(6);13-21, June 1994.

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{16} M. Kaspar, P. Schaumont, I. Bolsens, and H. De Man. Incremental hardware address generation. In Proc. Workshop on Design Methodologies for Microelectronics, pages 153- 159, 1995.

Cited By

Taniguchi IJayapala MRaghavan PCatthoor FSakanushi KTakeuchi YImai MWakabayashi K(2009)Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processorsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509742(449-454)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509742

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cover image ACM Conferences

EDTC '97: Proceedings of the 1997 European conference on Design and Test

March 1997

596 pages

ISBN:0818677864

Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 17 March 1997

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EDTC96: European Design and Test Conference

March 17 - 20, 1997

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Cited By

Taniguchi IJayapala MRaghavan PCatthoor FSakanushi KTakeuchi YImai MWakabayashi K(2009)Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processorsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509742(449-454)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509742

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