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Register Synthesis for Speculative Computation

Published: 17 March 1997 Publication History

Abstract

Speculative computation and branch prediction have been used in high-performance processor design for many years. Recently, it has also been applied to high-level synthesis where a priori knowledge of possible control paths provides an even higher performance potential. One problem of speculative techniques is the circuit overhead necessary for correctness preservation. While in processors, overhead is high due to the required generality, high-level synthesis can, again, employ a priori knowledge. The paper presents a register synthesis and allocation technique for speculative computation with branch prediction which is based on life time trees. It creates shift register structures with little register and control overhead.

References

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[1] J. Hennessy, D. Patterson Computer architecture - A quantitative approach. 2nd Ed., Morgan-Kaufmann, 1996.
[2]
[2] U. Holtmann, R. Ernst Combining MBP-Speculative Computation and Loop Pipelining in High-Level Synthesis, EDAC'95, pp. 550-555.
[3]
[3] U. Holtmann, R. Ernst Speculative Computation for Coprocessor Synthesis, Proc. ICCD '93; pp. 126-131, 1993.
[4]
[4] A. Sharma, R. Jain Register Estimation from Behavioral Specifications, Proc. ICCD '94; S. 576-580, 1995.
[5]
[5] K. Wakabayaschi, H. Tanaka Global Scheduling Independent of Control Dependencies Based on Condition Vectors, Proc. DAC 1992, pp. 112-115.

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cover image ACM Conferences
EDTC '97: Proceedings of the 1997 European conference on Design and Test
March 1997
596 pages
ISBN:0818677864

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IEEE Computer Society

United States

Publication History

Published: 17 March 1997

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  1. high-level-synthesis
  2. life time analysis
  3. register synthesis
  4. speculative computation

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