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Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations

Published: 22 September 2002 Publication History

Abstract

This paper investigates the usage of floating-point arithmetic on FPGAs for N-Body simulation in natural science. The common aspect of these applications is the simple computing structure where forces between a particle and its surrounding particles are summed up. The role of reduced precision arithmetic is discussed, and our implementation of a floating-point arithmetic library with parameterized operators is presented. On the base of this library, implementation strategies of complex arithmetic units are discussed. Finally the realization of a fully pipelined pressure force calculation unit consisting of 60 floating-point operators with a resulting performance of 3.9 Gflops on an off the shelf FPGA is presented.

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  • (2016)The Unified Accumulator ArchitectureACM Transactions on Reconfigurable Technology and Systems10.1145/28094329:3(1-23)Online publication date: 20-May-2016
  • (2013)Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision supportMicroelectronics Journal10.1016/j.mejo.2013.02.02144:5(421-430)Online publication date: 1-May-2013
  • (2013)VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba TechniqueCircuits, Systems, and Signal Processing10.1007/s00034-012-9457-332:1(15-27)Online publication date: 1-Feb-2013
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  1. Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations

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    cover image Guide Proceedings
    FCCM '02: Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
    September 2002
    ISBN:076951801X

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    IEEE Computer Society

    United States

    Publication History

    Published: 22 September 2002

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    View all
    • (2016)The Unified Accumulator ArchitectureACM Transactions on Reconfigurable Technology and Systems10.1145/28094329:3(1-23)Online publication date: 20-May-2016
    • (2013)Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision supportMicroelectronics Journal10.1016/j.mejo.2013.02.02144:5(421-430)Online publication date: 1-May-2013
    • (2013)VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba TechniqueCircuits, Systems, and Signal Processing10.1007/s00034-012-9457-332:1(15-27)Online publication date: 1-Feb-2013
    • (2010)Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable ComputingACM Transactions on Reconfigurable Technology and Systems10.1145/1862648.18626503:4(1-25)Online publication date: 1-Nov-2010
    • (2010)VFloatACM Transactions on Reconfigurable Technology and Systems10.1145/1839480.18394863:3(1-34)Online publication date: 1-Sep-2010
    • (2010)High-throughput bayesian computing machine with reconfigurable hardwareProceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723127(73-82)Online publication date: 21-Feb-2010
    • (2007)Parallel implementation of Cholesky LLT-algorithm in FPGA-based processorProceedings of the 7th international conference on Parallel processing and applied mathematics10.5555/1786194.1786211(137-147)Online publication date: 9-Sep-2007
    • (2006)Rapid development of high performance floating-point pipelines for scientific simulationProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1899135(191-191)Online publication date: 25-Apr-2006
    • (2005)64-bit floating-point FPGA matrix multiplicationProceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays10.1145/1046192.1046204(86-95)Online publication date: 20-Feb-2005
    • (2004)An Analysis of the Cost Effectiveness of an Adaptable Computing ClusterCluster Computing10.1023/B:CLUS.0000039495.40522.de7:4(357-371)Online publication date: 1-Oct-2004

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